Displaying 2 results from an estimated 2 matches for "getcommonsuperregclass".
2012 May 14
0
[LLVMdev] Register coalescing (Subregs and SuperRegs)
...ter pair R3:R2 i.e %D0 in the hexagon backend. The question is this
possible in the current setup of the Reg. Coalescer and the Reg. Allocator
? Or is there some target hook that'll help me inform the Register coalescer
or the allocator ?
@Jakob: I noticed your commit last week regarding
TRI::getCommonSuperRegClass(). Can that have a role to play here?
FWIW, the relevant patterns for COMBINE_rr are shown below.
------------------------------------------------------------------
// Combine.
let isPredicable = 1, neverHasSideEffects = 1 in
def COMBINE_rr : ALU32_rr<(outs DoubleRegs:$dst),
(ins...
2013 Jun 19
1
[LLVMdev] Register coalescer and reg_sequence (virtual super-regs)
Was it the subreg lane masks / mapping that was added to address the missed
coalescing? This solution is nice, but I don't think it'll work for me. I
have 8-element vector registers that can be grouped into virtual super regs
for bulk save/restore, and as soon as I have more than 4 in a tuple, the
unsigned int used to hold the lane masks overflows and switches over to the
"bit 31 set