search for: getcachelinesize

Dear LLVM contributors, I work on the "Improvement of vectorization process in Polly". At the moment I'm trying to implement tiling, interchanging and unrolling of specific loops based on the following algorithm for the analytical modeling [1]. It requires information about the following parameters of a target architecture: 1. Size of double-precision floating-point number. 2.

Hi, I am new to llvm, and recently am playing with opt. I want to use opt to apply one optimization pass to a .bc file. However, I encounter some problems which I failed to find the answers on the internet. Any suggestions are highly appreciated. Question 1: For example, I issued the following command $: opt-trunk -si-lower-control-flow t.c_00.bc -o t.c_01.bc Then I got the following

Thank you! Is this information available programmatically through some LLVM API, so that next time some hardware manufacturer does some crazy experiment, my code can be automatically compatible with it as soon as LLVM is? Le 11/03/2017 à 13:38, Bruce Hoult a écrit : > PowerPC G5 (970) and all recent IBM Power have 128 byte cache lines. I > believe Itanium is also 128. > > Intel

...4 .td files? The current > design doesn't capture heterogeneity at all, not because we're not > interested but simply because our compiler captures that at a higher > level outside of LLVM. AFAIK it is not handled at all. Any architecture that supports big.LITTLE will return 0 on getCacheLineSize(). See AArch64Subtarget::initializeProperties(). > > * write-back / write-through write buffers > > Do you mean for caches, or something else? https://en.wikipedia.org/wiki/Cache_%28computing%29#Writing_policies Basically, with write-though, every store is a non-temporal store (Or...

Hi, thank you for sharing the system hierarchy model. IMHO it makes a lot of sense, although I don't know which of today's passes would make use of it. Here are my remarks. I am wondering how one could model the following features using this model, or whether they should be part of a performance model at all: * ARM's big.LITTLE * NUMA hierarchies (are the NUMA domains