Displaying 3 results from an estimated 3 matches for "getcachelevel".
2018 Nov 02
2
RFC: System (cache, etc.) model for LLVM
...ever be reuse" a
non-temporal memory access.
In the the latter interpretation, what does "number of streams" mean?
AFAIU the processer will just queue memory operations (e.g. for
writing to RAM). Is it the maximum number of operations in the queue?
> >> The intent is that getCacheLevel(0) is the L1 cache, getCacheLevel(1) is
> >> the L2 cache and so on.
> >
> > Can passes rely on it?
>
> Yes.
Naively, I'd put Blue Gene/Q's L1P cache between the L1 and the L2,
i.e. the L1P would be getCacheLevel(1) and getCacheLevel(2) would be
L2. How would yo...
2018 Nov 01
3
RFC: System (cache, etc.) model for LLVM
...at
runtime via a hardware register. It supports 3 settings:
* Interpret every memory access as start of a stream
* Interpret a stream when there are 2 consecutive cache misses
* Only establish streams via dcbt instructions.
> >> class TargetMemorySystemInfo {
> >> const TargetCacheLevelInfo &getCacheLevel(unsigned Level) const;
> >>
> >> /// getNumLevels - Return the number of cache levels this target has.
> >> ///
> >> unsigned getNumLevels() const;
> >>
> >> /// Cache level iterators
> >> ///...
2018 Nov 01
2
RFC: System (cache, etc.) model for LLVM
...tire cache lines,
e.g. dcbz on PowerPC, but it requires the cache line to be correct.
Also see https://www.mono-project.com/news/2016/09/12/arm64-icache/
* Instruction cache
Am Di., 30. Okt. 2018 um 15:27 Uhr schrieb David Greene via llvm-dev
<llvm-dev at lists.llvm.org>:
> class TargetCacheLevelInfo {
> /// getWays - Return the number of ways.
> ///
> unsigned getWays() const;
That is, associativity?
Bandwidth might be a useful addition, e.g. if a performance analysis
tools uses the roofline model.
> class TargetSoftwarePrefetcherInfo {
> /// Should we...