Displaying 3 results from an estimated 3 matches for "getbranchtargetopvalue".
2018 Mar 26
0
wrong imm value for branch conditions..
...*def BGEID : TBT<0b101110, (outs), (ins GR32:$ra, brtarget:$offset),
"bgeid\t$ra,$offset", [], IIC_BRc> {*
* let rd = 0b10101;*
*}*
*def brtarget : Operand<OtherVT>*
*{*
* let PrintMethod = "printPCRelImmOperand";*
* let EncoderMethod = "getBranchTargetOpValue";*
* let OperandType = "OPERAND_PCREL";*
* let DecoderMethod = "DecodeBranchTarget";*
*}*
*getBranchTargetOpValue**(const MCInst &MI, unsigned OpNo,*
* SmallVectorImpl<MCFixup> &Fixups,*
* const MCSubtarg...
2011 Oct 10
2
[LLVMdev] Adding fixups and relocations late in code generation
...In our case, the backend produces an expression for the branch which is
the target label. I make a call from the .td for the branch instruction
which calls a routine in MipsMCCodeEmmitter.cpp. That routine
##############################################################
unsigned MipsMCCodeEmitter::
getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups) const {
const MCOperand &MO = MI.getOperand(OpNo);
if (MO.isReg()) {
unsigned Reg = MO.getReg();
unsigned RegNo = getMipsRegisterNumbering(Reg);
return RegNo;
} else if (MO.isImm()) {...
2011 Oct 10
0
[LLVMdev] Adding fixups and relocations late in code generation
...ces an expression for the branch which is
> the target label. I make a call from the .td for the branch instruction
> which calls a routine in MipsMCCodeEmmitter.cpp. That routine
>
> ##############################################################
> unsigned MipsMCCodeEmitter::
> getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
> SmallVectorImpl<MCFixup> &Fixups) const {
>
> const MCOperand &MO = MI.getOperand(OpNo);
>
> if (MO.isReg()) {
> unsigned Reg = MO.getReg();
>
> unsigned RegNo = getMipsRegisterNumbering(Reg);
> ret...