Displaying 2 results from an estimated 2 matches for "getbitsspillalignment".
2004 Aug 27
2
[LLVMdev] PrologEpilogInserter question
Hello,
after some time I'm trying to build my code with the current CVS of LLVM, and
have a problem. The mentioned file, around line 184, contains:
if (FixedSlot == FixedSpillSlots+NumFixedSpillSlots) {
// Nope, just spill it anywhere convenient.
FrameIdx = FFI->CreateStackObject(RegInfo->getSpillSize(Reg)/8,
2004 Aug 27
0
[LLVMdev] PrologEpilogInserter question
...ment' returns
> 4, which becomes 0 after division.
Oh, it looks that backends now should specify register size in bits. I've
updated my code, but it would be nice if 'getSpillAlignment' encode this
information in the name, for example 'getSpillAlignmentInBits' or
'getBitsSpillAlignment'.
- Volodya