search for: getbinarycodeforinstr

Hi, *case MICROBLAZE::BGEID:* * {* * // op: raencoder* * op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);* * Value |= (op & UINT64_C(31)) << 16;* * // op: imm16* * op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); -> should be operand[1]* * Value |= op & UINT64_C(65535);* * break;* * }* I have added

Hi, It seems like CodeEmitterGen gets confused when we use named suboperands. sample code: def memsrc : Operand<i16> { let PrintMethod = "printSrcMemOperand"; let MIOperandInfo = (ops GR16:$ra, i16imm:$imm_i16); let ParserMatchClass = memAsmOperand; } def LOAD16m : Inst32rri<0x0, (outs GR16:$rb), (ins memsrc:$src2), "ldi16 {$rb,

...6: asm tags for .s emission Currently, movt/movw emission works correctly in .s, but not in .o emission This lead me to believe that the correct place to put the code to handle MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path was to place a case in getMachineOpValue() (i.e. not ARMMCCodeEmitter::getBinaryCodeForInstr like I mistakenly wrote in my prior email.) Are you implying that the movt/movw instruction definition in the .td files need to be fixed up instead to declare a new special case for .o emission via the EncoderMethod string, for the .o emission of movt/movw to be considered "correct"? (If...

...hey even mostly kept the instruction formats! Can I tell tablegen to have two encodings and switch between them using a predicate? I do not want to create new instructions (e.g. ADD_KCPSM3 and ADD_KCPSM6). If that is not possible I will just dump the tablegen's *GenCodeEmitter.inc file with the getBinaryCodeForInstr() and write it by hand. I guess this is the only place where opcodes are used? (I do not use LLVM's MC disassembler.) Cheers, Jara -- Space--the final frontier! http://linkedin.com/in/jaroslavsykora

...CGenCodeEmitter.inc" But PPCCodeEmitter.inc: namespace llvm { ... } // end llvm namespace As result LLVM build terminate with error: /usr/home/wanderer/pkg/build/llvm/obj/lib/Target/PowerPC/PPCGenCodeEmitter.inc:11: error: definition of 'unsigned int<unnamed>::PPCCodeEmitter::getBinaryCodeForInstr(llvm::MachineInstr&)' is not in namespace enclosing '<unnamed>::PPCCodeEmitter' After adding "namespace llvm {" in AlphaCodeEmitter.cpp gcc 4.1.0 terminate build with error: /home/wanderer/pkg/build/llvm/src/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp:76: error: ex...

...the register, to know what register this returned value represents I should refer to MipsGenRegisterInfo.td, that’s where I think the mapping happens. However, inside the MipsCodeEmitter class there is a method that returns the binary encoding of the machine instruction (uint64_t MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI)). That’s why I thought about activating the code emitter during post-ra would solve my problem if that’s even possible. Thanks, - Jafar J. From: Jim Grosbach Sent: Thursday, May 30, 2013 8:49 PM To: Jafar J Cc: llvmdev at cs.uiuc.edu ; Mailing List Subject: Re:...

...CC 4.1.0 (GCC CVS mainline version). 1) Build terminate with error: llvm[3]: Compiling SparcV8CodeEmitter.cpp for Debug build /usr/home/wanderer/pkg/build/llvm/obj/lib/Target/SparcV8/SparcV8GenCodeEmitter.inc:11: error: definition of 'unsigned int llvm::<unnamed>::SparcV8CodeEmitter::getBinaryCodeForInstr(llvm::MachineInstr&)' is not in namespace enclosing 'llvm::<unnamed>::SparcV8CodeEmitter' gmake[3]: *** [/usr/home/wanderer/pkg/build/llvm/obj/lib/Target/SparcV8/Debug/SparcV8CodeEmitter.o] Error 1 Problem in including SparcV8GenCodeEmitter.inc: namespace llvm { ... #in...

...er, to know what register this returned value represents I should refer to MipsGenRegisterInfo.td, that’s where I think the mapping happens. > > However, inside the MipsCodeEmitter class there is a method that returns the binary encoding of the machine instruction (uint64_t MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI)). That’s why I thought about activating the code emitter during post-ra would solve my problem if that’s even possible. > > Thanks, > - Jafar J. > > From: Jim Grosbach > Sent: Thursday, May 30, 2013 8:49 PM > To: Jafar J > Cc: llvmdev at c...

...he register, to know what register this returned value represents I should refer to MipsGenRegisterInfo.td, that’s where I think the mapping happens. However, inside the MipsCodeEmitter class there is a method that returns the binary encoding of the machine instruction (uint64_t MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI)). That’s why I thought about activating the code emitter during post-ra would solve my problem if that’s even possible. Thanks, - Jafar J. From: Jim Grosbach Sent: Thursday, May 30, 2013 8:49 PM To: Jafar J Cc: llvmdev at cs.uiuc.edu ; Mailing List Su...

....inc: > > namespace llvm { > ... > } // end llvm namespace > > As result LLVM build terminate with error: > > /usr/home/wanderer/pkg/build/llvm/obj/lib/Target/PowerPC/PPCGenCodeEmitter.inc:11: > error: definition of 'unsigned > int<unnamed>::PPCCodeEmitter::getBinaryCodeForInstr(llvm::MachineInstr&)' is > not in namespace enclosing '<unnamed>::PPCCodeEmitter' > > After adding "namespace llvm {" in AlphaCodeEmitter.cpp > gcc 4.1.0 terminate build with error: > /home/wanderer/pkg/build/llvm/src/llvm/lib/Target/Alpha/AlphaCodeEm...

...now what register this returned value represents I should refer to MipsGenRegisterInfo.td, that’s where I think the mapping happens. >> >> However, inside the MipsCodeEmitter class there is a method that returns the binary encoding of the machine instruction (uint64_t MipsCodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI)). That’s why I thought about activating the code emitter during post-ra would solve my problem if that’s even possible. >> >> Thanks, >> - Jafar J. >> >> From: Jim Grosbach >> Sent: Thursday, May 30, 2013 8:49 PM >> To: J...

On Mon, 24 Oct 2005, Vladimir A. Merzliakov wrote: > I have some problems with build current CVS version LLVM using GCC 4.1.0 (GCC > CVS mainline version). Thanks! > 1) Build terminate with error: > > llvm[3]: Compiling SparcV8CodeEmitter.cpp for Debug build > /usr/home/wanderer/pkg/build/llvm/obj/lib/Target/SparcV8/SparcV8GenCodeEmitter.inc:11: > error: definition of

Thanks, that helps. The code emitter is definitely not the way you want to go about solving this problem, though. Are the instruction opcode (MachineInstr::getOpcode()) and the operand values not sufficient? All the information present in the encoding should be inferable from those, as that’s where the encoding comes from. -Jim On May 30, 2013, at 10:12 AM, Jafar J <pluck90 at

...ut the ARMCodeEmitter wasn't updated to compensate. emitPseudoInstruction() asserts (llvm_unreachable). 3) FCONSTS/FCONSTD also assert similarly. emitMiscInstruciton which used to support these instructions was removed in r116644. If you try to add back a case for them in the obvious way, getBinaryCodeForInstr() (which now ostensibly should handle this and has a case for it) asserts constructing the instruction because getMachineOpValue(MI, MI,getOperand(1)) doesn't handle a MachineOperand of type FPImm. I'm not sure what the right way to fix these last to issues is. Is any regression testing d...

I need to represent each instruction with its (32-bit) binary encoding, and I reached to a conclusion that I could get the encoding through the MipsCodeEmitter. What I’m trying to do exactly is write a scheduler which tries to minimize the switching activity between the scheduled instructions in each basic block. One way to do that is by representing each instruction with its complete binary

..."JIT relocation model must be set to static or default!"); > + > + MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>()); > do { > MovePCtoLROffset = 0; > MCE.startFunction(MF); > @@ -101,6 +108,9 @@ > default: > MCE.emitWordBE(getBinaryCodeForInstr(*I)); > break; > + case TargetInstrInfo::LABEL: > + MCE.EmitLabel(MI.getOperand(0).getImm()); > + break; > case PPC::IMPLICIT_DEF_GPRC: > case PPC::IMPLICIT_DEF_G8RC: > case PPC::IMPLICIT_DEF_F8: > Index: lib/Target/X86/X86CodeEmitter.cpp &...

...st be set to static or default!"); >> + >> + MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>()); >> do { >> MovePCtoLROffset = 0; >> MCE.startFunction(MF); >> @@ -101,6 +108,9 @@ >> default: >> MCE.emitWordBE(getBinaryCodeForInstr(*I)); >> break; >> + case TargetInstrInfo::LABEL: >> + MCE.EmitLabel(MI.getOperand(0).getImm()); >> + break; >> case PPC::IMPLICIT_DEF_GPRC: >> case PPC::IMPLICIT_DEF_G8RC: >> case PPC::IMPLICIT_DEF_F8: >> Index: lib...

Hi everyone, Here's a patch that enables exception handling when jitting. I've copy/pasted _many_code from lib/Codegen/DwarfWriter.cpp, so we may need to factorize it, but the functionality is there and I'm very happy with it :) lli should now be able to execute the output from llvm-gcc when using exceptions (the UnwindInst instruction is not involved in this patch). Just add the

..."JIT relocation model must be set to static or default!"); > + > + MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>()); > do { > MovePCtoLROffset = 0; > MCE.startFunction(MF); > @@ -101,6 +109,9 @@ > default: > MCE.emitWordBE(getBinaryCodeForInstr(*I)); > break; > + case TargetInstrInfo::LABEL: > + MCE.emitLabel(MI.getOperand(0).getImm()); > + break; > case PPC::IMPLICIT_DEF_GPRC: > case PPC::IMPLICIT_DEF_G8RC: > case PPC::IMPLICIT_DEF_F8: > Index: lib/Target/X86/X86CodeEmitter.cpp >...

Dear all, Here's a new patch with Evan's comments (thx Evan!) and some cleanups. Now the (duplicated) exception handling code is in a new file: lib/ExecutionEngine/JIT/JITDwarfEmitter. This patch should work on linux/x86 and linux/ppc (tested). Nicolas -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: jit-exceptions.patch URL: