search for: getapintvalue

...ly at the code in comment 5 of PR15581, is that the pre-decrement case? > I can't test that case on PPC, so I can certainly believe that there is a problem somewhere. > The relevant code is a little farther down: > > APInt OV = > cast<ConstantSDNode>(Offset)->getAPIntValue(); > if (AM == ISD::PRE_DEC) > OV = -OV; > > ConstantSDNode *CN = > cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx)); > APInt CNV = CN->getAPIntValue(); > if (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx ==...

...-decrement. Looking briefly at the code in comment 5 of PR15581, is that the pre-decrement case? I can't test that case on PPC, so I can certainly believe that there is a problem somewhere. The relevant code is a little farther down: APInt OV = cast<ConstantSDNode>(Offset)->getAPIntValue(); if (AM == ISD::PRE_DEC) OV = -OV; ConstantSDNode *CN = cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx)); APInt CNV = CN->getAPIntValue(); if (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) CNV += OV; else CNV...

Hello Hal, I have a strong suspicion that your constant folding optimization introduced at r174746 is broken on ARM. There is a bug about it: http://llvm.org/bugs/show_bug.cgi?id=15581 There is no such issue with 3.2, and reverting r174746 on top of r178740 also fixes the problem. I'm trying to fix it myself, but still have no good ideas; so it would be great to have an advice from you.

...(revision 191902) +++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp (working copy) @@ -3415,12 +3415,16 @@ // (*ext (rotr x, (sub 32, y))) SDValue LArgExtOp0 = LHSShiftArg.getOperand(0); EVT LArgVT = LArgExtOp0.getValueType(); - if (LArgVT.getSizeInBits() == SUBC->getAPIntValue()) { - SDValue V = - DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, LArgVT, - LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAmt); - return DAG.getNode(LHSShiftArg.getOpcode(), DL, VT, V).getNode(); - } + bool HasROTRWithLArg = TL...

...eads to your troubles later on. It would seem that the truncate is created by: TargetLowering::SimplifySetCC ... if (N0.getOpcode() == ISD::SETCC && isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); if (TrueWhenTrue) return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); // Invert the condition. ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType().isInteger());...

...that the truncate is created by: > > TargetLowering::SimplifySetCC > > ... > > > if (N0.getOpcode() == ISD::SETCC && > isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { > bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ > (N1C->getAPIntValue() != 1); > if (TrueWhenTrue) > return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); > > // Invert the condition. > ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); > CC = ISD::getSetCCInverse(CC, > > N0.getOpera...

...MVT::Other, Chain, Tmp, N2); > } > } > > if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { > bool Equal = false; > if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) > if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && > Op0.getOpcode() == ISD::XOR) { > TheXor = Op0.getNode(); > Equal = true; > } > > SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; > > EVT SetCCVT = NodeToReplace.getVa...

...N->getDebugLoc(), MVT::Other, Chain, Tmp, N2); } } if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { bool Equal = false; if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && Op0.getOpcode() == ISD::XOR) { TheXor = Op0.getNode(); Equal = true; } SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; EVT SetCCVT = NodeToReplace.getValueType(); if (LegalTypes)...

...-------- next part -------------- Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp (revision 165638) +++ lib/Target/X86/X86ISelLowering.cpp (working copy) @@ -14418,6 +14418,7 @@ if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { CC = X86::GetOppositeBranchCondition(CC); std::swap(TrueC, FalseC); + std::swap(TrueOp, FalseOp); } // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. @@ -14500,6 +14501,45 @@ } }...

...hain, Tmp, N2); >> } >> } >> >> if (Op0.getOpcode() != ISD::SETCC&& Op1.getOpcode() != ISD::SETCC) { >> bool Equal = false; >> if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) >> if (RHSCI->getAPIntValue() == 1&& Op0.hasOneUse()&& >> Op0.getOpcode() == ISD::XOR) { >> TheXor = Op0.getNode(); >> Equal = true; >> } >> >> SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; >> >>...

On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > >> Our architecture has 1-bit boolean predicate registers. >> >> I've defined comparison >> >> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>;

On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > Our architecture has 1-bit boolean predicate registers. > > I've defined comparison > > > def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; > > > > > But then I end up having the following bug: > >

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...2.getNode()); - if ((Tmp1C && Tmp1C->isNullValue()) || - (Tmp2C && Tmp2C->isNullValue() && - (CCCode == ISD::SETLE || CCCode == ISD::SETGE || - CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) || - (Tmp2C && Tmp2C->getAPIntValue() == 1 && - (CCCode == ISD::SETLT || CCCode == ISD::SETGT || - CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { - // low part is known false, returns high part. - // For LE / GE, if high part is known false, ignore the low part. - // For LT / GT,...