Displaying 4 results from an estimated 4 matches for "get_value_when_ready".
2013 Jul 31
2
[LLVMdev] Intended semantics for ``fence seq_cst``
struct {
volatile int flag;
int value;
} s;
int get_value_when_ready() {
while (s.flag) ;
__sync_synchronize();
return s.value;
}
This is "valid" legacy code on some processors, yet it's not valid to
replace __sync_synchronize with an atomic_thread_fence because, in
theory, LLVM could hoist the load of s.value. In practice it currently
doesn'...
2013 Jul 31
0
[LLVMdev] Intended semantics for ``fence seq_cst``
2013/7/31 JF Bastien <jfb at google.com>:
> Hi,
>
> TL;DR: should we add a new memory ordering to fences?
>
>
> ``fence seq_cst`` is currently use to represent two things:
> - GCC-style builtin ``__sync_synchronize()`` [0][1].
> - C11/C++11's sequentially-consistent thread fence
> ``std::atomic_thread_fence(std::memory_order_seq_cst)`` [2].
>
> As far
2013 Aug 01
0
[LLVMdev] Intended semantics for ``fence seq_cst``
...mory model would apply, and I don't think the instructions emitted
would change at all on the platforms I'm familiar with.
Jeffrey
On Wed, Jul 31, 2013 at 4:15 PM, JF Bastien <jfb at google.com> wrote:
> struct {
> volatile int flag;
> int value;
> } s;
>
> int get_value_when_ready() {
> while (s.flag) ;
> __sync_synchronize();
> return s.value;
> }
>
> This is "valid" legacy code on some processors, yet it's not valid to
> replace __sync_synchronize with an atomic_thread_fence because, in
> theory, LLVM could hoist the load of s.va...
2013 Jul 31
2
[LLVMdev] Intended semantics for ``fence seq_cst``
Hi,
TL;DR: should we add a new memory ordering to fences?
``fence seq_cst`` is currently use to represent two things:
- GCC-style builtin ``__sync_synchronize()`` [0][1].
- C11/C++11's sequentially-consistent thread fence
``std::atomic_thread_fence(std::memory_order_seq_cst)`` [2].
As far as I understand:
- The former orders all memory and emits an actual fence instruction.
- The