search for: gergo

Displaying 20 results from an estimated 90 matches for "gergo".

Did you mean: ergo
2010 Feb 05
0
[LLVMdev] Integrated instruction scheduling/register allocation
...quires handling of physical register dependencies in those schedulers, which I am currently struggling with. It's all in a very messy pre-prototype stage, but I'm getting there and will be happy to contribute my work when it's nice and clean. Thanks for the feedback, Jakob and Evan. Gergo -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria...
2010 Feb 06
1
[LLVMdev] Integrated instruction scheduling/register allocation
...ulers, which I am currently struggling with. It's > all in a very messy pre-prototype stage, but I'm getting there and will be > happy to contribute my work when it's nice and clean. Sounds great. Thanks. Evan > > Thanks for the feedback, Jakob and Evan. > > > Gergo > -- > Gergö Barany, research assistant gergo at complang.tuwien.ac.at > Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ > Vienna University of Technology Tel: +43-1-58801-58522 > Argentinierstrasse 8/E185, 104...
2010 Feb 04
2
[LLVMdev] Integrated instruction scheduling/register allocation
A more pressing need is a pre-regalloc scheduler that can switch modes to balance reducing latency vs. reducing register pressure. The problem is the current approach is the scheduler is locked into one mode or the other. For x86, it generally makes sense to schedule for low register pressure. That is, until you are dealing with a block that are explicitly SSE code in 64-bit mode. In that case,
2012 Jun 18
0
[LLVMdev] Is cross-compiling for ARM on x86 with llvm/Clang possible?
...ny documentation on how to > do it? Dunno. Last time I looked, the documentation of clang's command line flags disagreed with reality, and the -ccc-host-triple flag wasn't documented anywhere. This might have changed in the meantime. -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598
2010 Aug 29
0
[LLVMdev] [Query] Programming Register Allocation
...ought, does LLVM place casts into > different virtual registers, or do I need to include casting of floats to > integers or vice versa when I see ADD i32 float i32? The instruction selector creates all necessary conversion instructions. -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria Fax: +43-1-58801-18598
2010 Aug 29
1
[LLVMdev] [Query] Programming Register Allocation
...++time; } else { assert( 0 && "The register is always defining or used." ); } } } } } } Thanks, Jeff Kunkel On Sun, Aug 29, 2010 at 8:45 AM, Gergö Barany <gergo at complang.tuwien.ac.at>wrote: > On Sat, Aug 28, 2010 at 16:20:42 -0400, Jeff Kunkel wrote: > > What I need to know is how to access the machine register classes. Also, > I > > need to know which virtual register is to be mapped into each specific > > register class. I...
2006 Dec 07
0
Session Progress Transmission to Phone
...t-Length: 237 v=0 o=AudiocodesGW 283013199 283012901 IN IP4 216.187.142.190 s=Phone-Call c=IN IP4 216.187.142.190 t=0 0 m=audio 6350 RTP/AVP 0 101 a=rtpmap:0 PCMU/8000 a=rtpmap:101 telephone-event/8000 a=fmtp:101 0-15 a=ptime:20 a=sendrecv Doug. > -----Original Message----- > From: Csibra Gergo [mailto:gergo@csibra.hu] > Sent: Thursday, December 07, 2006 12:17 PM > To: gsalas@manta.telconet.net; Asterisk Users Mailing List - > Non-Commercial Discussion > Subject: Re: [asterisk-users] FXO USB that works with Asterisk? > > > Thursday, December 7, 2006, 7:40:09 PM, Gui...
2008 Jun 10
2
mac address in prompt
Hi there, for some reasons bash writes out my host's mac address as a result of including \h in PS1. Do you know why? This was not always so. [gergoe at x0-13-xx-xx-xx-xx ~]$ echo $PS1 [\u@\h \W]\$ - Gergely
2010 Aug 28
2
[LLVMdev] [Query] Programming Register Allocation
So I have a good understanding of what and how I want to do in the abstract sense. I am starting to gain a feel for the code base, and I see that I may have a allocator up and running much faster than I once thought thanks to the easy interfaces. What I need to know is how to access the machine register classes. Also, I need to know which virtual register is to be mapped into each specific
2017 May 22
2
How exactly is datatype alignment determined?
On Mon, 22 May 2017, Dr. ERDI Gergo wrote: > Actually, tracking down the sequence of function calls, it turns out that '8' > is ultimately coming from the following call in DataLayout::getAlignment: > > getAlignmentInfo(AGGREGATE_ALIGN, 0, abi_or_pref, Ty); > > this seems to return 8 with the following dat...
2017 May 07
3
Instruction selection for 'load' based on static vs. dynamic data
...entptr inbounds %S, %S* %0, i16 0, i32 0 %2 = load i8, i8* %1, align 1 ret i8 %2 } So my question is, what kind of pattern matching can I do in my 'lpm' and 'ld' instructions that it would be able to make a distinction about these two usecases? Thanks, Gergo -- .--= ULLA! =-----------------. \ http://gergo.erdi.hu \ `---= gergo at erdi.hu =-------' Have you heard about the new OO COBOL language? "ADD 1 TO COBOL GIVING COBOL"
2017 May 30
1
Pseudo-instruction that overwrites its input register
...of their operands being both an input and an output. So the idea is that you specify your `outs` in the instruction definition, one of those will have a `RegConstraint` on them and finally, you emit these nodes in your <TargetName>ISelDAGToDAG.cpp. On Tue, May 30, 2017 at 3:01 PM, Dr. ERDI Gergo <gergo at erdi.hu> wrote: > On Tue, 30 May 2017, Nemanja Ivanovic wrote: > > This is typically accomplished with something like PPC's `RegConstraint` >> and >> `NoEncode`. You can see examples of it that are very similar to what >> you're after in >>...
2008 Sep 23
2
chan_misdn troubles
Hello I have just set up Asterisk Asterisk 1.4.21.2 on a CentOS 5.2 machine. I am using the OpenVox B200P ISDN card. My problem is that even though chan_misdn module seems to be loaded correctly with Asterisk (I can see it using 'module show' command) the misdn commands are not available to me in the CLI so I cannot tell if my box is correctly interfacing with the ISDN card Any ideas
2012 Oct 11
0
[LLVMdev] RegisterClass constraints in TableGen
Excellent, I've implemented my own PBQP register allocator and solved the issue very painlessly. Now onto those more interesting problems! Thanks for your suggestion, Fraser On Fri, Oct 5, 2012 at 9:26 AM, Gergö Barany <gergo at complang.tuwien.ac.at>wrote: > On Thu, Oct 04, 2012 at 16:20:53 +0100, Fraser Cormack wrote: > > This architecture has two single-ported register files. Each instruction > > can only read one operand from each register file, but can write to > either. > > Even if you...
2008 Sep 18
1
how to detect pickup...
Hello asterisk-users, My SIP phones are in pickupgroup, and if some of them ringing from other phone can pick up with *8 as usual. But I want to know if this happen. I've tried the a extension, but seems not working. Any other idea? -- Best regards, Gergo mailto:csibra at gmail.com
2017 May 22
2
How exactly is datatype alignment determined?
...The target datalayout specifies that pointers are aligned to 8 bits (i.e. unaligned), so I would expect getPrefTypeAlignment to return 1: target datalayout = "e-S8:p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8" So where does that datatype alignment result of 8 come from? Thanks, Gergo
2010 Jul 06
2
Y-cords - What are they ?
Good Afternoon, Can someone please explain what Y-cords are available out there and how they can be used with Aastra or other VoIP phones? Maybe with or WITHOUT headsets? Isn't a Y-cord traded for soft Barge in these days? Thanks, Bruce -------------- next part -------------- An HTML attachment was scrubbed... URL:
2017 Aug 26
2
Unaligned atomic load/store
...and llc finishes, generating not-obviously-wrong machine code, so there doesn't seem to be anything further downstream breaking because of this. So my questions are: * What is the purpose of this assertion? * What is the right way to handle this situation in an unaligned target? Thanks, Gergo
2010 Feb 03
2
[LLVMdev] Integrated instruction scheduling/register allocation
...ailing list archives and the LLVM source code, but I haven't found anything suggesting that this has been done. If anyone has tried it and would be willing to share code, insights, or lessons learned, I would be very grateful to hear from them. [1] http://www.llvm.org/devmtg/2008-08/ Thanks, Gergo -- Gergö Barany, research assistant gergo at complang.tuwien.ac.at Institute of Computer Languages http://www.complang.tuwien.ac.at/gergo/ Vienna University of Technology Tel: +43-1-58801-58522 Argentinierstrasse 8/E185, 1040 Wien, Austria...
2004 Feb 02
4
extconf.rb patch
...Why not automagically delete generated header files like this? File.open("Makefile","ab+"){|f| f.puts f.puts("tclean:; @$(RM) "+(Dir[''*.t''].map{|fn| fn.sub(''.t'',''.h'')}.join)) f.puts } Reduces user error :) Gergo -- +-[ Kontra, Gergely<kgergely@mcl.hu> PhD student Room IB113 ]---------+ | http://www.mcl.hu/~kgergely "Olyan langesz vagyok, hogy | | Mobil:(+36 20) 356 9656 ICQ: 175564914 poroltoval kellene jarnom" | +-- Magyar php mirror es magyar php dokumentacio: http://hu.php...