search for: genri

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2014 Jul 31
3
[LLVMdev] initialize register attributes in instruction definition
...ister_num let HWEncoding{8} = SC_X; let HWEncoding{9} = SC_Y; ….. }” can I set up the input/ouput register flags like this? or some other way in codegen to make the register flags are set up based on the instructions? let Constraints = “$dst.SC_X =1, $src.SC_Y =0" in { def GENri : my_instr <op, 0, (outs GPR_V4_R32:$dst), (ins GPR_V4_R32:$src), !strconcat(asmstr, " $dst, ""$src"), [(set v4i32:$dst, (node v4i32:$src)]>; } tks...
2014 Aug 01
2
[LLVMdev] initialize register attributes in instruction definition
...tion related). Then I can directly access it for the machine instruction emit. That would be nice. Tks kevin > This is something that the R600 backend does a lot. Take a look at > lib/Target/R600/ R600RegisterInfo.td and R600Instructions.td > > -Tom > >> { >> def GENri : my_instr <op, 0, (outs GPR_V4_R32:$dst), (ins GPR_V4_R32:$src), >> !strconcat(asmstr, " $dst, ""$src"), >> [(set v4i32:$dst, (node v4i32:$src)]>; >> >> } >> &gt...