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Media instructions like - parallel add and subtract, Sign/Zero Extend and Add instructions seem to be missing from ARM target support. These instructions are not listed in GenInstrNames.inc Kapil On Fri, Oct 10, 2008 at 11:54 AM, Evan Cheng <evan.cheng at apple.com> wrote: > > Can you give some examples of missing instructions? > > Evan > > On Oct 9, 2008, at 4:58 PM, kapil anand wrote: > >> I have a question regarding ARM support. It was ment...

On Oct 10, 2008, at 2:07 PM, kapil anand wrote: > Media instructions like - parallel add and subtract, Sign/Zero > Extend and Add instructions seem to be missing from ARM target > support. These instructions are not listed in GenInstrNames.inc These would be best supported by adding builtins to llvm-gcc and adding intrinsics to llvm. Some of them could be implemented as <2 x i16> operations as well. Any help to implement this support would be great, -Chris

...e backend. Just to illustrate what I am trying to do, the first thing I thought about how to achieve this was to group instruction definitions in InstrInfo.td in the order of categories, and to put pseudo instructions in between to mark category boundaries. However, the Target Instruction Enum in GenInstrNames.inc does not follow the definition order of the .td, but is in fact ordered alphabetically. Thanks for any suggestions! Christian -- CONFIDENTIAL NOTICE: The contents of this message, including any attachments, are confidential and are intended solely for the use of the person or...

...;clattner at apple.com> wrote: > > On Oct 10, 2008, at 2:07 PM, kapil anand wrote: > > > Media instructions like - parallel add and subtract, Sign/Zero > > Extend and Add instructions seem to be missing from ARM target > > support. These instructions are not listed in GenInstrNames.inc > > These would be best supported by adding builtins to llvm-gcc and > adding intrinsics to llvm. Some of them could be implemented as <2 x > i16> operations as well. > > Any help to implement this support would be great, > > -Chris > __________________________...

...nc.tmp): \ $(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir $(Echo) "Building $(<F) register info implementation with tblgen" - $(Verb) $(TableGen) -gen-register-desc -o $@ $< + $(Verb) $(TableGen) -gen-register-desc -o $(call SYSPATH, $@) $< $(TARGET:%=$(ObjDir)/%GenInstrNames.inc.tmp): \ $(ObjDir)/%GenInstrNames.inc.tmp : %.td $(ObjDir)/.dir $(Echo) "Building $(<F) instruction names with tblgen" - $(Verb) $(TableGen) -gen-instr-enums -o $@ $< + $(Verb) $(TableGen) -gen-instr-enums -o $(call SYSPATH, $@) $< $(TARGET:%=$(ObjDir)/%GenInstrInfo.in...

Can you give some examples of missing instructions? Evan On Oct 9, 2008, at 4:58 PM, kapil anand wrote: > I have a question regarding ARM support. It was mentioned in mails > below that LLVM supports ARM v6 but a lot of ARM v6 instructions are > actually missing from ARM ISA description files( e.g. Media > Instructions). Is there any documentation mentioning the unsupported

I have a question regarding ARM support. It was mentioned in mails below that LLVM supports ARM v6 but a lot of ARM v6 instructions are actually missing from ARM ISA description files( e.g. Media Instructions). Is there any documentation mentioning the unsupported parts of v6 version Thanks --Kapil On Thu, Sep 18, 2008 at 2:14 PM, Evan Cheng <evan.cheng at apple.com> wrote: > > On

Reid, I think it is the first time it is run that the errors occcur !? Not sure but that would seem logical. Aaron