search for: genericscheduler

...s you can. So I think the challenge is how to expose the > generic scheduler's functionality as a base class or composition of > utilities so that defining your strategy doesn't require too much > copy-paste. ​Isn't GCNMaxOccupancySchedStrategy [1] already an example on using GenericScheduler as the base class? [1] http://llvm.org/doxygen/classllvm_1_1GCNMaxOccupancySchedStrategy.html -- Wei-Ren Chen (陳韋任) Homepage: https://people.cs.nctu.edu.tw/~chenwj -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attach...

..., but not much. The post-ra scheduler simply doesn't have enough freedom to move instructions around once physical registers have been assigned, so I contend that MachineScheduler needs to consider latency. I've looked at what's going on in the debugger and the problem seems to be that GenericSchedulerBase::setPolicy does not set Policy.ReduceLatency because it thinks that the other zone (Top in this case) is issue limited. There are lots of things I don't understand here: 1. "Issue limited" seems to mean that the number of instructions is greater than the length of the critical pa...

...ounts[PIdx]; As for "shouldReduceLatency should not be relevant at MicroOpBufferSize = 1": are you suggesting that shouldReduceLatency should effectively be changed to always return true on in-order CPUs? Even with that change, latency comes pretty far down the list of criteria tested in GenericScheduler::tryCandidate. Thanks, Jay. On Mon, 9 Sep 2019 at 19:36, Andrew Trick <atrick at apple.com> wrote: > > > > On Sep 9, 2019, at 4:22 AM, Jay Foad <jay.foad at gmail.com> wrote: > > > > Hi, > > > > I'm trying to understand why MachineScheduler does...

...t machine. > The abstract pipeline is built around the notion of an "issue point". This is merely a reference point for counting machine cycles. > > > IssueWidth is meant to be a hard in-order constraint (we sometimes call this kind of constraint a "hazard"). In the GenericScheduler strategy, no more than IssueWidth micro-ops can ever be scheduled in a particular cycle. > > In practice, IssueWidth is useful to model to the bottleneck between the decoder (after micro-op expansion) and the out-of-order reservation stations. If the total number of reservation stations is al...

...e model distinguishes between in-order constraints and out-of-order constraints so that the target's scheduling strategy can apply appropriate heuristics. For a well-balanced CPU pipeline, out-of-order resources would not typically be treated as a hard scheduling constraint. For example, in the GenericScheduler, a delay caused by limited out-of-order resources is not directly reflected in the number of cycles that the scheduler sees between issuing an instruction and its dependent instructions. In other words, out-of-order resources don't directly increase the latency between pairs of instructions. Ho...

...to move x86 and armv7 ASAP. Leaving it disabled is becoming more of a maintenance burden. Please see my llvm-dev list messages to Ghassan yesterday. MI Scheduler is pass that just provides a place to do scheduling and a large toolbox to do it with. ScheduleDAGMI is a list scheduler driver, and the GenericScheduler strategy attempts to balance register pressure with latency. In my opinion getting the right register pressure vs latency balance is easy to do at a given point in time for a small benchmark suite, but very, very hard to do in general with a design that works across microarchitectures and is resili...

...ving it disabled is becoming more of a maintenance > burden. > > > Please see my llvm-dev list messages to Ghassan yesterday. MI Scheduler is > pass that just provides a place to do scheduling and a large toolbox to do > it with. ScheduleDAGMI is a list scheduler driver, and the GenericScheduler > strategy attempts to balance register pressure with latency. In my opinion > getting the right register pressure vs latency balance is easy to do at a > given point in time for a small benchmark suite, but very, very hard to do > in general with a design that works across microarchite...

...On Fri, Oct 21, 2016 at 10:29 AM, Ehsan Amiri <ehsanamiri at gmail.com> wrote: > You can do this by changing instruction scheduling heuristics. I think the > more important question is if this correct always for all platforms. > > I don't know which scheduler you use. We use GenericScheduler and > PostGenericScheduler before and after RA. These classes have a > ::tryCandidate method which compares two instructions that can be legally > scheduled and decide which of the two should be scheduled. Currently these > method are target independent. > > The correctness questi...

Hi, I would like to ask what IssueWidth and NumMicroOps refer to in MachineScheduler, just to be 100% sure what the intent is. Are we modeling the decoder phase or the execution stage? Background: First of all, there seems to be different meanings of "issue" depending on which platform you're on:

Hello. Is there a way to specify in the back end an (ISD::INLINEASM) SDNode to be scheduled first under all circumstances? I need to specify something like node priority to schedule the node before all other nodes in the SelectionDAG of the basic block. (Using chain or glue edges in order to make a node first is not a good idea, since I am doing this at instruction selection time, on

Hi, Andrew, Thank you for answering my question. What's the status of misched? is it experimental? I found it is disabled by default for all architectures(3.4svn). I also don't understand the algorithm. Could you point to me more papers or text materials about your approach? it seems that you want to balance register pressure and ILP in misched. On Tue, Sep 24, 2013 at 4:07 PM,

...SAP. Leaving it disabled is becoming more of a maintenance burden. > > > > Please see my llvm-dev list messages to Ghassan yesterday. MI Scheduler is pass that just provides a place to do scheduling and a large toolbox to do it with. ScheduleDAGMI is a list scheduler driver, and the GenericScheduler strategy attempts to balance register pressure with latency. In my opinion getting the right register pressure vs latency balance is easy to do at a given point in time for a small benchmark suite, but very, very hard to do in general with a design that works across microarchitectures and is resili...

...t; The abstract pipeline is built around the notion of an "issue point". This is merely a reference point for counting machine cycles. >> >> >> IssueWidth is meant to be a hard in-order constraint (we sometimes call this kind of constraint a "hazard"). In the GenericScheduler strategy, no more than IssueWidth micro-ops can ever be scheduled in a particular cycle. >> >> In practice, IssueWidth is useful to model to the bottleneck between the decoder (after micro-op expansion) and the out-of-order reservation stations. If the total number of reservation stati...

...ignificant > performance penalty if you use more than a certain amount. Do any of > the MachineSchedulers support switching into an 'optimize for register > pressure mode' once it detects register pressure above a certain limit? The code in ConvergingScheduler (I’ll rename it to GenericScheduler soon) is meant to demonstrate most of the features so developers can copy what they need into their own strategy, add heuristics and change the underlying data structures, which often makes sense. You can decide whether you want only bottom-up, top-down, or both. For an in-order processor, I think...

Hi, I'm working on defining a SchedMachineModel for the Southern Islands family of GPUs, and I have two questions related to the MachineScheduler. 1. I have a resource that can process 15 instructions at the same time. In the TableGen definitions, should I do: def HWVMEM : ProcResource<15>; or let BufferSize = 15 in { def HWVMEM : ProcResource<1>; } 2. Southern Islands has

On Thu, Mar 26, 2015 at 11:50:20PM -0700, Andrew Trick wrote: > > > On Mar 26, 2015, at 7:36 PM, Tom Stellard <tom at stellard.net> wrote: > > > > Hi, > > > > I have a program with over 100 loads (each with a 10 cycle latency) > > at the beginning of the program, and I can't figure out how to get > > the machine scheduler to intermix ALU

...;) () #10 0x0000000001a29a2c in llvm::FPPassManager::runOnModule(llvm::Module&) () #11 0x0000000001a2a28f in llvm::legacy::PassManagerImpl::run(llvm::Module&) () With these mixed in from time to time: #0 0x0000000001850825 in llvm::SUnit::ComputeDepth() () #1 0x00000000017d22a4 in llvm::GenericScheduler::registerRoots() () #2 0x00000000017c9002 in llvm::ScheduleDAGMI::initQueues(llvm::ArrayRef<llvm::SUnit*>, llvm::ArrayRef<llvm::SUnit*>) () #3 0x00000000017c9439 in llvm::ScheduleDAGMILive::initQueues(llvm::ArrayRef<llvm::SUnit*>, llvm::ArrayRef<llvm::SUnit*>) () #4 0x000...

Hello List! I am looking at top-down vs. bottom-up list scheduling for simple(r) in-order cores. First, for some context, below is a fairly representative pseudo-code example of the sort of DSP-like codes I am looking at: uint64_t foo(int *pA, int *pB, unsigned N, unsigned C) { uint64_t sum = 0; while (N-- > 0) { A1 = *pA++; A2 = *pA++; B1 = *pB++; B2 =

...gy. It would be natural to handle nop insertion within your implementation. In fact, the interpretation of most machine model properties (MircoOpBufferSize, resource BufferSize, ResourceCycles, ResourceDelay) is handled within the MachineSchedStrategy. In past emails I have been explaining how the GenericScheduler interprets the model, but it is really up to your custom strategy to implement the model. > I have attached a patch that adds the 'ResourceDelays' field in tablegen. Could you have a look at it? A couple possible issues are: > - 'Delay' is signed, since 'Cycles' in MC...

...nable it only during postRA scheduling. -Andy > Pete >> >> In fact, the interpretation of most machine model properties (MircoOpBufferSize, resource BufferSize, ResourceCycles, ResourceDelay) is handled within the MachineSchedStrategy. In past emails I have been explaining how the GenericScheduler interprets the model, but it is really up to your custom strategy to implement the model. >> >>> I have attached a patch that adds the 'ResourceDelays' field in tablegen. Could you have a look at it? A couple possible issues are: >>> - 'Delay' is signed, sin...