Displaying 4 results from an estimated 4 matches for "generalpurposeregclass".
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
...ld I partition them
into different RegisterClasses so that I can easy define the
instruction?
All RegisterClasses must be mutally exclusive. That is, a register can
only be in a RegisterClass. Otherwise TableGen will raise an error
message.
def ReadOnlyRegClass : RegisterClass<...>;
def GeneralPurposeRegClass : RegisterClass<...>;
def WriteOnlyRegClass : RegisterClass<...>;
def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
GeneralPurposeRegClass :$src), "mov $dest, $src">;
There can be only one RegisterClass defined for each instruction
operand, but actually t...
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
...-Chien Chiu wrote:
> I' have three set of registers - read-only regs, general purpose regs
> (read and write), and write-only regs. How should I partition them
> into different RegisterClasses so that I can easy define the
> instruction?
[snip]
> def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
> GeneralPurposeRegClass :$src), "mov $dest, $src">;
>
> There can be only one RegisterClass defined for each instruction
> operand, but actually the destition operand could be
> 'GeneralPurposeRegClass ' or 'WriteOnlyRegClass ', and the source...
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
...' have three set of registers - read-only regs, general purpose regs
> > (read and write), and write-only regs. How should I partition them
> > into different RegisterClasses so that I can easy define the
> > instruction?
> [snip]
> > def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
> > GeneralPurposeRegClass :$src), "mov $dest, $src">;
> >
> > There can be only one RegisterClass defined for each instruction
> > operand, but actually the destition operand could be
> > 'GeneralPurposeRegClass ' or 'WriteOnlyRegCla...
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
...set of registers - read-only regs, general purpose regs
>>> (read and write), and write-only regs. How should I partition them
>>> into different RegisterClasses so that I can easy define the
>>> instruction?
>> [snip]
>>> def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
>>> GeneralPurposeRegClass :$src), "mov $dest, $src">;
>>>
>>> There can be only one RegisterClass defined for each instruction
>>> operand, but actually the destition operand could be
>>> 'GeneralPurposeRegClass ' or '...