Displaying 8 results from an estimated 8 matches for "generalpurposerc".
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
...re floating point registers, and the others are integer
registers.
I typedef two packed classes: [4 x float] and [4 x int], and add an
enum 'packed' to MVT::ValueType (ValuesTypes.h).
I declared all 'RegisterClass'es to be 'packed' (first argument of
RegisterClass):
def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>;
def INT_ReadOnlyRC : RegisterClass<packed, 128, [I0, I1]>;
def FP_ReadOnlyRC : RegisterClass<packed, 128, [F0, F1]>;
def MOVgg : BinaryInst<0x51, (
ops GeneralPurposeRC :$dest,
ope GeneralPurposeRC :$src), "mov $dest...
2005 Jul 25
2
[LLVMdev] How to partition registers into different RegisterClass?
...estination register
// of any instruction hereafter.
%r1 = add %Vec4 v1, c1
%r2 = mul %Vec4 v1, c2
%o1 = mul %Vec4 r2, v2 // write the output register 'o1'
I planed to partition the register into different RegisterClass:
input, output, general purpose, constant, etc.
def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>;
def InputRC : RegisterClass<packed, 128, [V0, V1]>;
def ConstantRC : RegisterClass<packed, 128, [C0, C1]>;
def ADDgg : BinaryInst<0x51, (
ops GeneralPurposeRC :$dest,
ope GeneralPurposeRC :$src), "add $dest, $src">...
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
On Fri, Jul 22, 2005 at 10:29:38AM +0800, Tzu-Chien Chiu wrote:
> I' have three set of registers - read-only regs, general purpose regs
> (read and write), and write-only regs. How should I partition them
> into different RegisterClasses so that I can easy define the
> instruction?
[snip]
> def MOV : BinaryInst<2, (ops GeneralPurposeRegClass :$dest,
>
2005 Jul 22
2
[LLVMdev] How to partition registers into different RegisterClass?
Hi, everyone.
I' have three set of registers - read-only regs, general purpose regs
(read and write), and write-only regs. How should I partition them
into different RegisterClasses so that I can easy define the
instruction?
All RegisterClasses must be mutally exclusive. That is, a register can
only be in a RegisterClass. Otherwise TableGen will raise an error
message.
def
2005 Jul 23
0
[LLVMdev] How to partition registers into different RegisterClass?
On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote:
> 2005/7/23, Chris Lattner <sabre at nondot.org>:
>> What does a 'read only' register mean? Is it a constant (e.g. returns
>> 1.0)? Otherwise, how can it be a useful value?
>
> Yes, it's a constant register.
>
> Because the instruction cannot contain an immediate value, a constant
> value may be stored in
2005 Jul 23
3
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/23, Chris Lattner <sabre at nondot.org>:
>
> What does a 'read only' register mean? Is it a constant (e.g. returns
> 1.0)? Otherwise, how can it be a useful value?
Yes, it's a constant register.
Because the instruction cannot contain an immediate value, a constant
value may be stored in a constant register, and it's defined _before_
the program starts by
2005 Jul 26
0
[LLVMdev] How to partition registers into different RegisterClass?
...the register allocator. The regalloc will eliminate the
virtual registers, assigning physical GPRs. This is what the 'allocation
order' is to cover.
> I planed to partition the register into different RegisterClass:
> input, output, general purpose, constant, etc.
>
> def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>;
> def InputRC : RegisterClass<packed, 128, [V0, V1]>;
> def ConstantRC : RegisterClass<packed, 128, [C0, C1]>;
The way you want to partition these is based on how the instruction set
works. If there is a single 'add' instr...
2005 Jul 22
0
[LLVMdev] How to partition registers into different RegisterClass?
...rs are integer
> registers.
>
> I typedef two packed classes: [4 x float] and [4 x int], and add an
> enum 'packed' to MVT::ValueType (ValuesTypes.h).
>
> I declared all 'RegisterClass'es to be 'packed' (first argument of
> RegisterClass):
>
> def GeneralPurposeRC : RegisterClass<packed, 128, [R0, R1]>;
> def INT_ReadOnlyRC : RegisterClass<packed, 128, [I0, I1]>;
> def FP_ReadOnlyRC : RegisterClass<packed, 128, [F0, F1]>;
...
> In the instruction selector, SDOperand::getValueType() always returns
> 'MVT::packed' for...