search for: gendagisel

Hi I am looking at some of the existing targets to try to understand more about writing a backend. I was a little puzzled by the use of a method ReplaceUses in *ISelDAGToDAG.cpp (*= most targets, e.g. ARM, X86..). I found its definition in the *GenDAGISel.inc file that is autogenerated from the target description. I can only assume TableGen emits this method definition for every traget. Is this method implementation, in some way that I cannot see, specific to a given target? I cannot see a reason for it not being a method of SelectionDAGISel...

...cific configuration. In such a case it would be nice if the MachineVerifier could detect this for me. Example predicate IsCore8 usage: def ADDx: BINOP<...>, Requires<[IsCore8]>; let Predicates=[IsCore8] in { def : SUBX: BINOP<...>; } The predicates are encoded into the targets GenDAGIsel file but not anywhere else that I can find: OPC_CheckPatternPredicate, 4, // (Subtarget.isCore8()) Thanks -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20190401/b46c6b83/attachment.html>

Hello. I come back to this older thread. Again, because of i64immSExt32 I receive TableGen error "Could not infer all types in, pattern!" (exact details written below). So far I'm not able to generate selection code with TableGen for the ADD_r* instructions, etc: def i64immSExt32 : PatLeaf<(imm), [{return

...ing testcase with -debug-only=isel and you'll see all the steps being > taken up to the moment of failure. The last few messages will be something > like "match failed at nnn". In your build directory in > lib/Target/<yourtarget> there will be a file <yourtarget>GenDAGISel.inc. > It contains the matching "script". The numbers nnn are shown in comments > in that file and correspond to the steps the matcher performs. You'll be > able to see what exactly it's trying to match. > > -Krzysztof > > > -- > Qualcomm Innovation Cen...

...:%=$(ObjDir)/%GenCodeEmitter.inc.tmp): \ $(ObjDir)/%GenCodeEmitter.inc.tmp: %.td $(ObjDir)/.dir $(Echo) "Building $(<F) code emitter with tblgen" - $(Verb) $(TableGen) -gen-emitter -o $@ $< + $(Verb) $(TableGen) -gen-emitter -o $(call SYSPATH, $@) $< $(TARGET:%=$(ObjDir)/%GenDAGISel.inc.tmp): \ $(ObjDir)/%GenDAGISel.inc.tmp : %.td $(ObjDir)/.dir $(Echo) "Building $(<F) instruction selector implementation with tblgen" - $(Verb) $(TableGen) -gen-dag-isel -o $@ $< + $(Verb) $(TableGen) -gen-dag-isel -o $(call SYSPATH, $@) $< $(TARGET:%=$(ObjDir)/%GenSub...

...through the path it takes when matching the AND node, and try to figure out why it ends up selecting the register-register version rather than the register-immediate version. Fortunately, the debug output from llc will contain a complete trace of what happened, so you just need to line it up with GenDAGISel.inc and determine which step did the wrong thing. At a guess, I'd say you probably have a type declared wrong somewhere. --Owen On Apr 19, 2012, at 4:05 PM, "Villmow, Micah" <Micah.Villmow at amd.com> wrote: > I'm not at the machine that has the changes, but it was fa...

Hi, I am having issues running a new backend that I created for a new architecture. I suspect these errors may have something to do with how I have the string setup in LLVMTargetMachine() below? Also - It would be great if someone could point me to a document that describes some of these error messages? For example what does t26 ..t4 mean? Thanks in advance for taking your valuable time to help

Hi there, I try to JIT compile some bitcode and seeing the following error: LLVM ERROR: Cannot select: 0x28ec830: ch,glue = X86ISD::CALL 0x28ec7c0, 0x28ef900, Register:i32 %EDI, Register:i8 %AL, RegisterMask:Untyped, 0x28ec7c0:1 0x28ef900: i32 = X86ISD::Wrapper TargetGlobalAddress:i32<void (i8*, ...)* @_ZN5FooBr7xprintfEPKcz> 0 0x28ec520: i32 = TargetGlobalAddress<void (i8*, ...)*

I'm not at the machine that has the changes, but it was failing at index 0. Micah From: Owen Anderson [mailto:resistor at mac.com] Sent: Thursday, April 19, 2012 3:35 PM To: Villmow, Micah Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] Tablegen to match a literal in an instruction Micah, I don't see anything wrong with this offhand. Have you tried getting the debug output

Hello, Im (trying) to write a backend for a simple 32bit processor architecture, with a single instruction format having no condition code registers. www.docm.mmu.ac.uk/STAFF/A.Nisbet/Sabre.pdf is the short 15 page document describing the architecture of Sabre. It is a Celoxica developed research/teaching processor, pages 5-8 contain relevant information for targetting it from a new compiler

Hello. I'm having problems at instruction selection with my back end with the following basic-block due to a vector add with immediate constant vector (obtained by vectorizing a simple C program doing vector sum map): vector.ph: ; preds = %vector.memcheck50 %.splatinsert = insertelement <8 x i64> undef, i64 %i.07.unr, i32 0