search for: genasmmatcher

I believe that table gen builds MipsGenAsmMatcher.inc which has the Match routines like MatchRegisterName(). In building MipsGenAsmMatcher.inc I am hitting the following issue (actually several, but they may be related). It may have something to do with the $$ escape sequence: /home/jcarter/workarea/llvm/lib/Target/Mips/Mips64InstrInfo.td:173:1:...

...the .inc file in my class for AsmParser. However, while building llvm, in linking stage for LTO, i am getting error - undefined reference to functions - ComputeAvailableFeatures, MatchInstructionImpl, MatchRegisterName and convertToMapAndConstraints. I see these functions declared and defined in GenAsmMatcher.inc file which i have included in my AsmParser class. Still i am getting the error. I may be missing something very basic. Can someone please help in resolving this error? Thanks. Regards, Alex -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm...

...the tablegen defs for many targets to denote instructions that a variable number of inputs, but it seems that there aren't any targets for which this results in variable elements in the instruction encoding (and thus in assembler parsing), since the tablegen generated assembly matcher ($(Target)GenAsmMatcher.inc) simply assumes that variable_ops are not to be parsed (match table: Convert_NoOperands). Now I understand that a variable length instruction is a weird concept for most CPUs, but we need it for at least one instruction in WebAssembly. We can probably hack around it in the WebAssemblyAsmParser...

...given register (in Mips $28 and $gp are the same) it would be quite useful for the llvm-mc assembler which has to handle cases where there are multiple names for the same register. A quick recursive grep shows that no target is currently using this. It is also not use when generating <target>GenAsmMatcher.inc. If this is the case, I will try and incorporate AltNames so the strings get correctly matched in the AsmMatcher. Cheers, Jack -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120211/0b223af9/attachment...

Hi, I'd like to modify MachineBasicBlock contents within a MachineFunctionPass on the basis of how many CPU cycles the assembly instructions corresponding to the MBB take. I'm using the AVR backend and the number of CPU cycles every AVR assembly operation takes is openly available. Is there any straightforward way of getting the opcode mnemonics corresponding to a MachineInstr? I've