Displaying 4 results from an estimated 4 matches for "genally".
2014 Feb 19
2
[LLVMdev] Question about per-operand machine model
Hi JinGu,
We currently have the ResourceCycles list to indicate the number of cpu cycles during which a resource is reserved. We could simply add a ResourceDelay with similar grammar. The MachineScheduler could be taught to keep track of the first and last time that a resource is reserved.
Note that the MachineScheduler will work with the instruction itineraries if you choose to implement them.
2014 Feb 28
2
[LLVMdev] Question about per-operand machine model
...ormations are not allowed
> any more, because hardware can not resolve resource conflict. There is a
> simple example as following:
>
> ADD dest_reg1, src_reg1, src_reg2 (functional unit : ALU)
> STORE dest_reg2, mem (functional unit: LOAD_STORE)
>
> These instructions can be genally packetized together because there is
> no dependency among operands and they use different functional unit. But
> we have one more restricton. The restriction is that some of
> instructions can not access to same register file at the same cycle. In
> other words, if 'src_reg1' o...
2014 Mar 03
2
[LLVMdev] Question about per-operand machine model
...hardware can not resolve resource conflict. There is a
>>> simple example as following:
>>>
>>> ADD dest_reg1, src_reg1, src_reg2 (functional unit : ALU)
>>> STORE dest_reg2, mem (functional unit: LOAD_STORE)
>>>
>>> These instructions can be genally packetized together because there is
>>> no dependency among operands and they use different functional unit. But
>>> we have one more restricton. The restriction is that some of
>>> instructions can not access to same register file at the same cycle. In
>>> othe...
2014 Mar 04
2
[LLVMdev] Question about per-operand machine model
...re is a
>>>>> simple example as following:
>>>>>
>>>>> ADD dest_reg1, src_reg1, src_reg2 (functional unit : ALU)
>>>>> STORE dest_reg2, mem (functional unit: LOAD_STORE)
>>>>>
>>>>> These instructions can be genally packetized together because there is
>>>>> no dependency among operands and they use different functional unit. But
>>>>> we have one more restricton. The restriction is that some of
>>>>> instructions can not access to same register file at the same cyc...