search for: gem5

Hi, I am trying to optimize some benchmarks using LLVM and run them on gem5 simulator (build for ARM). I am using Sourcery Codebench cross-compiler for ARM on my x-86 machine. My steps up till now have been using the following commands. 1. clang -static -emit-llvm -march=armv7-a -mfloat-abi=soft -target arm-elf a.cpp -c -integrated-as \ --sysroot=/home/silky/CodeSourc...

Hi All, I'm trying to compile clang+llvm on my desktop with cross-compiler to be able to work with llvm commands in ubuntu-arm image whithin gem5. If anybody has done this before I'd be so thankful to know the exact process and commands. I tried to configure llvm as follows but I couldn't get the arm-arm version correctly. To sum up, I need to cross-compile llvm for ARM to work in gem5 through the ubuntu image for ARM systems. ../ll...

Hi Silky, If I got correctly, you seem to be trying to run a bare-metal image on your model, but you compile with linux-gnueabi GCC. I don't know if that will make a difference, but I'd try to use none-eabi GCC toolchain and set the -target armv7a-none-eabi just in case. On 10 March 2013 00:26, Silky Arora <silkyar at umich.edu> wrote: > Most of the search results talk about

> It is done. Then, I should copy this version on my image and then boot the image with gem5. The > problem is when I try to run llvm-commands in gem5, they don't work and said : "cannot execute binary file". What does "file" says on the binary? > This means that I couldn't cross-compile the llvm for ARM to work on ARM! Something is broken on your side. I...

Hi all. tl;dr: I would like to add a long x86 instruction which doesn't conform to any existing format that I know; I'm not sure where to start. I am attempting to add an instruction into X86, to be simulated in gem5. I've already added a simple, opcode-only instruction which I can successfully decode and run in gem5, so I am roughly familiar with .td files and how backends are built out of them. My goal now is to make a more complex instruction -- specifically, I need to add large operands. The format wou...

On 03/18/2013 10:28 AM, Renato Golin wrote: > On 17 March 2013 22:40, SArora <silkyar at umich.edu > <mailto:silkyar at umich.edu>> wrote: > > However, this errors out saying > > /home/silky/VecProject/opencv/OpenCVInstall/arm/include/opencv2/core/mat.hpp:117:9: > error: cannot compile this atomic library call yet > CV_XADD(refcount, 1);

On 18 March 2013 09:43, Abdoulaye Walsimou Gaye <awg at embtoolkit.org> wrote: > ** > This is the same issue reported here > http://llvm.org/bugs/show_bug.cgi?id=15429 > Yes, it does look like the same problem, thanks! Silky, feel free to add your error messages to that bug to make sure it's taken into account when fixed. cheers, --renato -------------- next part

Thanks Renato and Giang. I was able to run a simple HelloWorld program on gem5 (in SE mode) by using -target -arm-none-linux-gnueabi as the option during cross compilation. I am trying to cross compile some Computer Vision algorithms, which use OpenCV libraries, and I tried using the same command line options - clang++ *-emit-llvm -static -c -Wall -g -O0 -mfpu=vfp -mfloa...

...mented a pass on LLVM backend that changes the output format of *ARM* assembly/binary (e.g add a jump at the end of each basic block to eliminate fall through). By calling: llc -march=arm somefile.bc it generates expected arm assembly/binary that runs properly on arm gnu linux (I use qemu-arm and gem5 to simulate it). Now I want to do the same thing on standard c library, but here are problems. Problems: According to: http://article.gmane.org/gmane.comp.compilers.llvm.devel/77025 https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_14/docs/OpenProjects.html#glibc compiling glibc using llvm may...

....llvm.org> wrote: > >> Hi all. >> >> tl;dr: I would like to add a long x86 instruction which doesn't conform >> to any existing format that I know; I'm not sure where to start. >> >> I am attempting to add an instruction into X86, to be simulated in gem5. >> I've already added a simple, opcode-only instruction which I can >> successfully decode and run in gem5, so I am roughly familiar with .td >> files and how backends are built out of them. >> >> My goal now is to make a more complex instruction -- specifically,...

On 17 March 2013 22:40, SArora <silkyar at umich.edu> wrote: > However, this errors out saying > > > /home/silky/VecProject/opencv/OpenCVInstall/arm/include/opencv2/core/mat.hpp:117:9: > error: cannot compile this atomic library call yet > CV_XADD(refcount, 1); > ^~~~~~~~~~~~~~~~~~~~ > >

...m-dev < llvm-dev at lists.llvm.org> wrote: > Hi all. > > tl;dr: I would like to add a long x86 instruction which doesn't conform to > any existing format that I know; I'm not sure where to start. > > I am attempting to add an instruction into X86, to be simulated in gem5. > I've already added a simple, opcode-only instruction which I can > successfully decode and run in gem5, so I am roughly familiar with .td > files and how backends are built out of them. > > My goal now is to make a more complex instruction -- specifically, I need > to add l...

...; >>> Hi all. >>> >>> tl;dr: I would like to add a long x86 instruction which doesn't conform >>> to any existing format that I know; I'm not sure where to start. >>> >>> I am attempting to add an instruction into X86, to be simulated in gem5. >>> I've already added a simple, opcode-only instruction which I can >>> successfully decode and run in gem5, so I am roughly familiar with .td >>> files and how backends are built out of them. >>> >>> My goal now is to make a more complex instructi...

>> > It is done. Then, I should copy this version on my image and then boot >> > the image with gem5. The >> > problem is when I try to run llvm-commands in gem5, they don't work and >> > said : "cannot execute binary file". >> What does "file" says on the binary? > when I use commands like : "#arm-linux-gnueabi-clang test.c -o test" or...

...ch of your time) I will try to generate it myself. I've found the definition of the "I" class at line 358 of llvm/lib/Target/X86/X86InstrFormats.td, which helps a lot. Let's assume I want to produce opcode 0x16 (which I'm using because it doesn't seem to be implemented in gem5 otherwise, and would simply produce a warning). Then my guess is that I should use something like: def CACHEADD : I<0x16, FORMAT, (outs), (ins), ASM, [(int_cache_add)]>, PD; where FORMAT comes from http://legup.eecg.utoronto.ca/doxygen/namespacellvm_1_1X86II.html and ASM =...

...try to generate it myself. I've found the definition of the > "I" class at line 358 of llvm/lib/Target/X86/X86InstrFormats.td, which > helps a lot. > > Let's assume I want to produce opcode 0x16 (which I'm using because it > doesn't seem to be implemented in gem5 otherwise, and would simply produce > a warning). Then my guess is that I should use something like: > def CACHEADD : I<0x16, FORMAT, (outs), (ins), > ASM, [(int_cache_add)]>, PD; > > where FORMAT comes from http://legup.eecg.utoronto.ca/doxygen/ > namespa...

Hello all. LLVM newbie here. If anything seems glaringly wrong with my use of LLVM, that's probably why. Here's what I'm trying to do. I have modified the gem5 simulator to accept a "new" x86 instruction. I've done this by just reserving the opcode in gem5's ISA specification, just as all other instructions are specified. I'm trying to get an LLVM backend to generate this opcode during code generation. My current plan is: 1. Dur...

..., RawFrm, (outs), (ins), "cache_op", [(int_cache_op)]>; I added this definition to llvm/lib/Target/X86/X86InstrInfo.td. I also had to comment out an instruction (PUSHES) which overlapped the 0x06 opcode. This was OK in my case (as far as I know) because PUSHES isn't implemented in gem5. Thanks again! Gus On Sun, Mar 18, 2018 at 11:30 PM, Craig Topper <craig.topper at gmail.com> wrote: > ASM is the text output you want printed in a textual listing of the > assembly. The curly braces you see in some text strings like > "adcx{l}\t{$src, $dst|$dst, $src}"...

...t. ~Craig On Sun, Mar 18, 2018 at 3:22 PM, Gus Smith via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Hello all. LLVM newbie here. If anything seems glaringly wrong with my use > of LLVM, that's probably why. > > Here's what I'm trying to do. I have modified the gem5 simulator to accept > a "new" x86 instruction. I've done this by just reserving the opcode in > gem5's ISA specification, just as all other instructions are specified. > > I'm trying to get an LLVM backend to generate this opcode during code > generation. My cur...

On Wed, Nov 21, 2012 at 8:02 PM, Anton Korobeynikov <anton at korobeynikov.info > wrote: > >> > It is done. Then, I should copy this version on my image and then boot > >> > the image with gem5. The > >> > problem is when I try to run llvm-commands in gem5, they don't work > and > >> > said : "cannot execute binary file". > >> What does "file" says on the binary? > > when I use commands like : "#arm-linux-gnueabi-clang...