search for: gdtr

Hi, Keir: the gdtr information in oldctx is an address for guest, not for vmxassist. When access descriptor on guest gdt, we need to go through guest page table if guest enable paging. This error may happen if guest enable PE/PG in one instruction. This patch fix this issue. Signed-off-by: Yunhong Jiang <yunho...

From: Tim Deegan <Tim.Deegan at cl.cam.ac.uk> Fix register constraints of final jump to kernel entry. When compiled with some GCC versions, mboot.c32 would clobber the kernel load address and try to jump to 0x2badb002. Signed-off-by: Tim Deegan <Tim.Deegan at cl.cam.ac.uk> --- --- syslinux-3.20-pre8/com32/modules/mboot.c.orig 2006-05-22 11:06:17.000000000 +0100 +++

...00000000030, SS - 0000000000000030 CR0 - 0000000080010033, CR2 - 0000000000000000, CR3 - 000000001FC01000 CR4 - 0000000000000668, CR8 - 0000000000000000 DR0 - 0000000000000000, DR1 - 0000000000000000, DR2 - 0000000000000000 DR3 - 0000000000000000, DR6 - 00000000FFFF0FF0, DR7 - 0000000000000400 GDTR - 000000001FBEEA98 0000000000000047, LDTR - 0000000000000000 IDTR - 000000001F6A9018 0000000000000FFF, TR - 0000000000000000 FXSAVE_STATE - 000000001FF13310 select help: !!!! X64 Exception Type - 0D(#GP - General Protection) CPU Apic ID - 00000000 !!!! ExceptionData - 0000000000000000 RIP - A...

> ah ha... now that I have all the pices in place, this is what I was missing: > > # EFI/BOOT/SYSLX64.CFG > # D-I config version 2.0 > # search path for the c32 support libraries (libcom32, libutil etc.) > PATH EFI/BOOT/SYSLINUX/EFI64/ > DEFAULT common > PROMPT 0 > LABEL common > CONFIG ../../syslinux.cfg ../../ > > The syslinux.cfg and all the other .cfg

On Thu, 17 Jan 2013 22:22:47 -0500 Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> wrote: > Jan had some comments about that patch: > > https://patchwork.kernel.org/patch/1745041/ > > Please fix it up so I can put it in the Linux tree. Please see below. Signed-off-by: Mukesh Rathor <mukesh.rathor@oracle.com> Thanks, Mukesh diff --git a/arch/x86/xen/xen-head.S

The current paravirt startup_ipi hook for vmware commit: ae5da273fe3352febd38658d8d34484cbcfb3423 is quite frankly ridiculous. In the middle of wake_up_secondary_cpu: We have: /* * Paravirt / VMI wants a startup IPI hook here to set up the * target processor state. */ startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, (unsigned

The current paravirt startup_ipi hook for vmware commit: ae5da273fe3352febd38658d8d34484cbcfb3423 is quite frankly ridiculous. In the middle of wake_up_secondary_cpu: We have: /* * Paravirt / VMI wants a startup IPI hook here to set up the * target processor state. */ startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, (unsigned

ioemu-remote: The device model needs to write in the ACPI tables when it wakes up from S3 state. Signed-off-by: Jean Guyader <jean.guyader@eu.citrix.com> -- Jean Guyader _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

...nal init/startup + IPI sequence, the BSP must issue the init IPI, a set application + processor state hypercall, followed by the startup IPI. + + The initial state contains the AP's control registers, general + purpose registers and segment registers, as well as the IDTR, + GDTR, LDTR and EFER. Any processor state not included in the initial + AP state (including x87 FPRs, SSE register states, and MSRs other than + EFER), are left in the poweron state. + + The BSP must construct the initial GDT used by each AP. The segment + register hidden state will be...

...nal init/startup + IPI sequence, the BSP must issue the init IPI, a set application + processor state hypercall, followed by the startup IPI. + + The initial state contains the AP's control registers, general + purpose registers and segment registers, as well as the IDTR, + GDTR, LDTR and EFER. Any processor state not included in the initial + AP state (including x87 FPRs, SSE register states, and MSRs other than + EFER), are left in the poweron state. + + The BSP must construct the initial GDT used by each AP. The segment + register hidden state will be...

...ormPei/AmdSev.c": > STATIC > VOID > AmdSevEsInitialize ( > VOID > ) > { > VOID *GhcbBase; > PHYSICAL_ADDRESS GhcbBasePa; > UINTN GhcbPageCount, PageCount; > RETURN_STATUS PcdStatus, DecryptStatus; > IA32_DESCRIPTOR Gdtr; > VOID *Gdt; > > if (!MemEncryptSevEsIsEnabled ()) { > return; > } > > PcdStatus = PcdSetBoolS (PcdSevEsIsEnabled, TRUE); > ASSERT_RETURN_ERROR (PcdStatus); > > // > // Allocate GHCB and per-CPU variable pages. > // Since the p...

...18, attr=0x0c093, limit=0xffffffff, base=0x0000000000000000 (XEN) ES: sel=0x0000, attr=0x1c000, limit=0xffffffff, base=0x0000000000000000 (XEN) FS: sel=0x0000, attr=0x1c000, limit=0xffffffff, base=0x0000000000000000 (XEN) GS: sel=0x0000, attr=0x1c000, limit=0xffffffff, base=0xffff880078800000 (XEN) GDTR: limit=0x0000007f, base=0xffff880078804000 (XEN) LDTR: sel=0x0000, attr=0x1c000, limit=0xffffffff, base=0x0000000000000000 (XEN) IDTR: limit=0x00000fff, base=0xffffffff81bb7000 (XEN) TR: sel=0x0040, attr=0x0008b, limit=0x00002087, base=0xffff88007...

...T (linear address, # ents) */ - unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */ + union { + struct { + /* PV: GDT (machine frames, # ents).*/ + unsigned long gdt_frames[16], gdt_ents; + } pv; + struct { + /* PVH: GDTR addr and size */ + unsigned long gdtaddr, gdtsz; + } pvh; + } u; unsigned long kernel_ss, kernel_sp; /* Virtual TSS (only SS1/SP1) */ /* NB. User pagetable on x86/64 is placed in ctrlreg[1]. */ unsigned long ctrlreg[8]; /* CR0-CR7 (control reg...

From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT

From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT

I have installed paltalk (chatting client) and it is working properly when it comes to hearing and talking. However, whenever I try to write, if I type one word no speace like "hello" i will have no problem. But if I was to type two words with as much as single space like "hello world" paltalk gives me the error below: Code: Alert: Your last text message was not sent because

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VMs (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VMs (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VM-s (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VM-s (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place