search for: gcn

Tim Northover via llvm-dev <llvm-dev at lists.llvm.org> writes: > Hi Varun, > > I'm definitely in favour of making -v more useful like this. > > On Thu, 12 Sep 2019 at 19:31, Varun Gandhi via llvm-dev > <llvm-dev at lists.llvm.org> wrote: >> Option 2 (less deviation from status quo): >> -v: Adopts behavior of -vvv from Option 1. :) >> -vv: Same

I installed CentOS on my home-server with 2 IDE 160GB MAXTOR HDD / RAID-1, LVM and ext3 partitions. Previous OS on this machine was FC2. I often "play" with LVM and, sometimes, have to extand or reduce some volumes size. I was surprised to see that resize2fs isn''t included anymore ! The replacing tool is ext2online but this one seems to only be able to grow a filesystem (not

...ib/Target/AMDGPU/SIISelLowering.cpp > +++ b/lib/Target/AMDGPU/SIISelLowering.cpp > @@ -263,6 +263,12 @@ SITargetLowering::SITargetLowering(TargetMachine &TM, > setOperationAction(ISD::FDIV, MVT::f32, Custom); > setOperationAction(ISD::FDIV, MVT::f64, Custom); > > + // GCN CMP_SWAP needs input marshalling, and output demarshalling > + setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); > + // We can't return success/failure, only the old value, > + // let LLVM add the comparison > + setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT...

Hi Tom, Matt, I'm working on a project that needs few coherent atomic operations (HSA mode: load, store, compare-and-swap) for std::atomic_uint in HCC. the attached patch implements atomic compare and swap for SI+ (untested). I tried to stay within what was available, but there are few issues that I was unsure how to address: 1.) it currently uses v2i32 for both input and output. This

...eration which is > faster but we haven't figured out how to operate it yet. I'm not aware > of a muladd version of fma on fermi and newer (GL 4.0). The tesla > series does have a floating point mul+add (but no fma). > Interesting. radeons seem to always have a unfused mad. pre-gcn parts apparently only have a 32bit fma with parts supporting double precision. The same restriction is stated for gcn parts in the isa docs, which obviously doesn't make sense, but I have no idea if the fma is full speed... Roland

...ttp://llvm.org/): LLVM version 3.7.1 Optimized build. Built Apr 4 2016 (15:04:44). Default target: x86_64-unknown-linux-gnu Host CPU: ivybridge Registered Targets: aarch64 - AArch64 (little endian) aarch64_be - AArch64 (big endian) amdgcn - AMD GCN GPUs arm - ARM arm64 - ARM64 (little endian) armeb - ARM (big endian) bpf - BPF (host endian) bpfeb - BPF (big endian) bpfel - BPF (little endian) cpp - C++ backend hexagon - He...

...c --version LLVM (http://llvm.org/): LLVM version 3.6.2 Optimized build with assertions. Built Aug 2 2015 (11:39:46). Default target: x86_64-apple-darwin15.4.0 Host CPU: core-avx2 Registered Targets: aarch64 - AArch64 (little endian) aarch64_be - AArch64 (big endian) amdgcn - AMD GCN GPUs arm - ARM arm64 - ARM64 (little endian) armeb - ARM (big endian) cpp - C++ backend hexagon - Hexagon mips - Mips mips64 - Mips64 [experimental] mips64el - Mips64el [experimental] mipsel - Mipsel ms...

> 1. In a CHECK-DAG group, don't let the matches for patterns overlap. > 2. Add a new CHECK-DAG-N directive, where N is some integer, to express > that a pattern must have N non-overlapping matches. I think #1 is much more intuitive and easy to describe/document than #2. Changing the meaning of DAG in that way is highly unlikely to affect any existing test, IMO. And if it does, my

...a gfid self-heal failed on <gfid:4a787ad7-ab91-46ef-9b31-715e49f5f818>/log/secure This still seems to be an INCREDIBLY fragile system. Why would it lock solid while copying a large file? Why no errors in the logs? I am the only one seeing this kind of behavior? sean -- Sean Fulton GCN Publishing, Inc. Internet Design, Development and Consulting For Today's Media Companies http://www.gcnpublishing.com (203) 665-6211, x203

...ount; there is no EXTRV. - NVPTX has SHF (https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-shf) with both left/right shift variants and with both "clamp" (clamps shift count at 32) and "wrap" (shift count taken mod 32) modes. - GCN has v_alignbit_b32 which is a right funnel shift, and it seems to be defined to take shift distances mod 32. based on that sampling, modulo behavior seems like a good choice for a generic IR instruction, and if you're going to pick one direction, right shifts are the one to use. Not sure ab...

...gt; Built Apr 4 2016 (15:04:44). >> Default target: x86_64-unknown-linux-gnu >> Host CPU: ivybridge >> >> Registered Targets: >> aarch64 - AArch64 (little endian) >> aarch64_be - AArch64 (big endian) >> amdgcn - AMD GCN GPUs >> arm - ARM >> arm64 - ARM64 (little endian) >> armeb - ARM (big endian) >> bpf - BPF (host endian) >> bpfeb - BPF (big endian) >> bpfel - BPF (little endian) &g...

Hi, Using FileCheck, I have not found a way to make a group of CHECK-DAG directives match multiple occurrences of a string. For example, I naively thought the following would match successfully: ``` $ cat checks.txt // CHECK: start // CHECK-DAG: foo // CHECK-DAG: foo // CHECK-DAG: bar // CHECK-NEXT: end $ cat input.txt start foo bar foo end $ FileCheck --input-file=input.txt checks.txt

...: num 25.6 215.4 41.7 239.4 30.5 ... $ Gtrockenmasseanteil : num 30.2 29.1 31.9 42.2 32.5 ... $ GtrockenmasseanteilanGesamt: num 78.8 98.3 86 96 76.5 ... $ GN : num 2.1 3.35 2.31 2.17 2.28 ... $ GC : num 43.8 45 44.9 43.6 43.5 ... $ GCN : num 20.9 13.4 19.4 20.1 19.1 ... $ Lfrischmasse : num 12.1 0 0 0 19 ... $ Ltrockenmasse : num 2.56 0 0 0 3.92 1.84 0 0 2.2 0 ... $ Ltrockenmasseanteil : num 21.2 0 0 0 20.7 ... $ LtrockenmasseanteilanGesamt: num 7.89 0 0 0 9.83 1.0...

...ies the input LLVM IR, which makes a second invocation for disassembly fail. An example patch to Mesa to test functionality is available here: https://gist.github.com/anonymous/6911363 -- Jay Cornwall -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm-r600-gcn-disassembly-in-elf.patch Type: text/x-diff Size: 6340 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20131009/0a583660/attachment.patch>

This looks like the right idea to me too. It may sound a bit weird to do that per instruction, but d3d11 does that as well. (Some d3d versions just have a global flag basically forbidding or allowing any such fast math optimizations in the assembly, but I'm not actually sure everybody honors that without tesselation...) For 1/9: Reviewed-by: Roland Scheidegger <sroland at vmware.com>

...4:44). > Default target: x86_64-unknown-linux-gnu > Host CPU: ivybridge > > Registered Targets: > aarch64 - AArch64 (little endian) > aarch64_be - AArch64 (big endian) > amdgcn - AMD GCN GPUs > arm - ARM > arm64 - ARM64 (little endian) > armeb - ARM (big endian) > bpf - BPF (host endian) > bpfeb - BPF (big endian) > bpfel...

...ed to do this, but >>>>>> I can think of a few concerns/questions. First of all, to implement >>>>>> the prefix scan, we'll need to do a code sequence that looks like >>>>>> this, modified from >>>>>> http://gpuopen.com/amd-gcn-assembly-cross-lane-operations/ (replace >>>>>> v_foo_f32 with the appropriate operation): >>>>>> >>>>>> ; v0 is the input register >>>>>> v_mov_b32 v1, v0 >>>>>> v_foo_f32 v1, v0, v1 row_shr:1 // Instruction...

...trinsics implemented that you need to do this, but >>>> I can think of a few concerns/questions. First of all, to implement >>>> the prefix scan, we'll need to do a code sequence that looks like >>>> this, modified from >>>> http://gpuopen.com/amd-gcn-assembly-cross-lane-operations/ (replace >>>> v_foo_f32 with the appropriate operation): >>>> >>>> ; v0 is the input register >>>> v_mov_b32 v1, v0 >>>> v_foo_f32 v1, v0, v1 row_shr:1 // Instruction 1 >>>> v_foo_f32 v1, v0, v1...

...o do >>>>>> this, but I can think of a few concerns/questions. First of all, >>>>>> to implement the prefix scan, we'll need to do a code sequence >>>>>> that looks like this, modified from >>>>>> http://gpuopen.com/amd-gcn-assembly-cross-lane-operations/ >>>>>> (replace >>>>>> v_foo_f32 with the appropriate operation): >>>>>> >>>>>> ; v0 is the input register >>>>>> v_mov_b32 v1, v0 >>>>>> v_foo_f32 v1, v0, v1...

...any non-zero number of threads after the master thread. If overlapping matches are not permitted, we must increase OMP_THREAD_LIMIT to at least 4 or reduce the number of pattern repetitions. S4. CHECK-DAG unneeded ---------------------- For example, test/CodeGen/AMDGPU/store-v3i64.ll has: ``` ; GCN-DAG: buffer_store_byte v ; GCN-DAG: buffer_store_byte v ; GCN-DAG: buffer_store_byte v ``` The intention appears to be the same as S3: match a pattern N times. However, this example doesn't actually need CHECK-DAG at all. First, all patterns in the group are the same, so they are not unordere...