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...de proper. -- Geoff Berry Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From: George Burgess [mailto:gbiv at google.com] Sent: Wednesday, April 20, 2016 3:29 PM To: Geoff Berry <gberry at codeaurora.org> Cc: Daniel Berlin <dberlin at dberlin.org>; llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [LICM][MemorySSA] Converting LICM pass to use MemorySSA to avoid AliasSet collapse issue Hi! > readonly calls are treated as clobbers by MemorySSA which leads...

...ussion. -- Geoff Berry Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From: Daniel Berlin [mailto:dberlin at dberlin.org] Sent: Wednesday, April 20, 2016 1:06 PM To: Geoff Berry <gberry at codeaurora.org>; George Burgess <gbiv at google.com> Cc: llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [LICM][MemorySSA] Converting LICM pass to use MemorySSA to avoid AliasSet collapse issue On Wed, Apr 20, 2016 at 9:58 AM, Geoff Berry <gberry at codeaurora.org...

Hi, I recently found myself in trouble because the crash I had disappeared with -g, so I could not debug the program. This happened because the optimizer did not remember to consider DBG_VALUEs instruction so it changed its behavior, and the bug went hiding. I then started discussing this on https://reviews.llvm.org/D45878, and since this is something that should be handled by all different

> On Aug 14, 2017, at 7:35 AM, Geoff Berry <gberry at codeaurora.org> wrote: > > Hi Sanjoy, > > [adding Adam since I believe he added the original FIXME to preserve SCEV > in LoopDataPrefetch] For record, that wasn’t me. It was there from the beginning when Hal added the PPC-specific pass. Adam > > On 8/14/2017 1:36 A...

...Access *M, -- Geoff Berry Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From: Daniel Berlin [mailto:dberlin at dberlin.org] Sent: Monday, April 11, 2016 4:17 PM To: Geoff Berry <gberry at codeaurora.org> Cc: llvm-dev <llvm-dev at lists.llvm.org>; Sanjoy Das <sanjoy at playingwithpointers.com>; Hal Finkel <hfinkel at anl.gov> Subject: Re: [LICM][MemorySSA] Converting LICM pass to use MemorySSA to avoid AliasSet collapse issue On Mon, Apr 11, 2016 at...

On 9/26/2017 6:47 PM, Matthias Braun wrote: > >> On Sep 26, 2017, at 3:33 PM, Geoff Berry <gberry at codeaurora.org >> <mailto:gberry at codeaurora.org>> wrote: >> >> >> >> On 9/26/2017 6:11 PM, Matthias Braun wrote: >>>> On Sep 26, 2017, at 2:39 PM, Geoff Berry via llvm-dev >>>> <llvm-dev at lists.llvm.org <mailto:llvm-dev...

...burgess.iv at gmail.com <mailto:george.burgess.iv at gmail.com>> > wrote: > > Yeah, that sounds like a fun bug. I'll take a look later today > and see what I can find out. :) > > On Fri, Apr 29, 2016 at 2:55 PM, Geoff Berry > <gberry at codeaurora.org <mailto:gberry at codeaurora.org>> wrote: > > Hi guys, > > I think I have run into another CachingMemorySSAWalker > cache bug. It's a bit tricky to reproduce, so I'd like to > start by trying to sho...

> On Sep 26, 2017, at 8:24 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On 9/26/2017 6:47 PM, Matthias Braun wrote: >>> On Sep 26, 2017, at 3:33 PM, Geoff Berry <gberry at codeaurora.org <mailto:gberry at codeaurora.org> <mailto:gberry at codeaurora.org <mailto:gberry at codeaurora.org>>> wrote: >>> >>> >>> >>> On 9/26/2017 6:11 PM, Matthias Braun wrote: >>>>> On Sep 26, 2017, at 2:39 PM, G...

...etting consistently written. On Mon, May 2, 2016 at 11:16 AM, George Burgess IV < george.burgess.iv at gmail.com> wrote: > Yeah, that sounds like a fun bug. I'll take a look later today and see > what I can find out. :) > > On Fri, Apr 29, 2016 at 2:55 PM, Geoff Berry <gberry at codeaurora.org> > wrote: > >> Hi guys, >> >> I think I have run into another CachingMemorySSAWalker cache bug. It's a >> bit tricky to reproduce, so I'd like to start by trying to show you what is >> happening when running EarlyCSE with my local ch...

...rds, what API do we provide for such use > cases. > > Also, what do we do with registers that don’t have definition? For > instance, a function live-ins register, a reserved register, and so on. > > Cheers, > -Quentin > > > On Oct 25, 2017, at 10:27 AM, Geoff Berry <gberry at codeaurora.org> wrote: > > > > Hi All, > > > > Currently, changing register assignments of definitions after register > allocation is not safe because there is no way to know which register > definitions were physical registers before RA (e.g. to meet ABI or ISA...

...of these. -- Geoff Berry Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From: Daniel Berlin [mailto:dberlin at dberlin.org] Sent: Friday, April 22, 2016 12:05 PM To: Geoff Berry <gberry at codeaurora.org> Cc: llvm-dev <llvm-dev at lists.llvm.org> Subject: Re: [llvm-dev] XDEBUG build bots? On Thu, Apr 21, 2016 at 1:18 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> > wrote: Hi All, Are there any bots that...

Hi All, I'm looking into converting LICM to use MemorySSA instead of AliasSets to determine when it is safe to hoist/sink/promote loads and stores to get around the issue of alias set collapse (see discussion [1]). I have a prototype implementation, but have run into two issues that I could use input from the designers of MemorySSA to resolve: 1) Is MemorySSA intended to be

Hi Geoff, On Wed, Aug 9, 2017 at 8:58 AM, Geoff Berry <gberry at codeaurora.org> wrote: > On 8/8/2017 8:38 PM, Sanjoy Das wrote: >> >> Hi, >> >> On Tue, Aug 8, 2017 at 12:58 PM, Friedman, Eli <efriedma at codeaurora.org> >> wrote: >>> >>> Oh, I see... yes, we do stupid things involving mutating NoWra...

...> > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux > Foundation Collaborative Project > > > > *From:* Daniel Berlin [mailto:dberlin at dberlin.org <dberlin at dberlin.org>] > *Sent:* Friday, April 22, 2016 12:05 PM > *To:* Geoff Berry <gberry at codeaurora.org> <gberry at codeaurora.org> > *Cc:* llvm-dev <llvm-dev at lists.llvm.org> <llvm-dev at lists.llvm.org> > *Subject:* Re: [llvm-dev] XDEBUG build bots? > > > > > > > > On Thu, Apr 21, 2016 at 1:18 PM, Geoff Berry via llvm-dev < &...

On 2018-02-22 11:14, gberry at codeaurora.org wrote: > FROM: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] ON BEHALF OF > Jun Lim via llvm-dev > SENT: Thursday, February 22, 2018 11:05 AM > > Hi All, > > I found some cases where a spill of a live range in a block is > reloaded only in one of i...

> On Sep 26, 2017, at 3:33 PM, Geoff Berry <gberry at codeaurora.org> wrote: > > > > On 9/26/2017 6:11 PM, Matthias Braun wrote: >>> On Sep 26, 2017, at 2:39 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org> wrote: >>> >>> Hi all, >>> >>> Mikael reported a machine verifi...

> From: junbuml at codeaurora.org [mailto:junbuml at codeaurora.org] > Sent: Thursday, February 22, 2018 11:39 AM > > On 2018-02-22 11:14, gberry at codeaurora.org wrote: > > FROM: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] ON BEHALF OF > > Jun Lim via llvm-dev > > SENT: Thursday, February 22, 2018 11:05 AM > > > > Hi All, > > > > I found some cases where a spill of a live range in a block...

...ot;you can ignore this path". The logic in the code that handles the former case only exists after the cache lookups, and so the first use properly detects that it can ignore this phi, and the second use , which just hits the cache, cannot. On Mon, Jun 27, 2016 at 10:27 AM, Geoff Berry <gberry at codeaurora.org> wrote: > Hey All, > > I've come across what I believe to be a bug in MemorySSA. George, I wasn't > sure if this was a known issue that you'll be addressing in your upcoming > walker caching changes or not, so I haven't investigated it very much....

On 9/26/2017 6:11 PM, Matthias Braun wrote: > >> On Sep 26, 2017, at 2:39 PM, Geoff Berry via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >> Hi all, >> >> Mikael reported a machine verification failure in his out-of-tree target with the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is:

Hey All, I've come across what I believe to be a bug in MemorySSA. George, I wasn't sure if this was a known issue that you'll be addressing in your upcoming walker caching changes or not, so I haven't investigated it very much. The test case is attached. The bug is that the defining access for the second load is set to the loop MemoryPhi node instead of being liveOnEntry as