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...? If it's not fixed, it's > probably better to create a new virtual register and use that > instead. It's not fixed. How do I create a new virtual register? This is my first real go at adding to LLVM, so I'm kind of figuring it out as I go along :) Cheers, Gary -- http://gbenson.net/

...error message that'd point me to where I need to start adding stuff, but I just got the cryptic: Cannot yet select: 0x10fc0500: ch = MemBarrier 0x10fc0368, 0x10fc0698, 0x10fc0610, 0x10fc0698, 0x10fc0698, 0x10fc0698". Can anyone point me in the right direction? Cheers, Gary -- http://gbenson.net/

...ter to create a new virtual register and use that >> instead. > > It's not fixed. How do I create a new virtual register? This is my > first real go at adding to LLVM, so I'm kind of figuring it out as I > go along :) > > Cheers, > Gary > > -- > http://gbenson.net/ > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

...t; >>works. > > > >Thanks for that. Attached is a working implementation of > >llvm.memory.barrier. > > > >>Thanks for doing this btw. > > > >No problem, I need it! ;) > > > >Cheers, > >Gary > > > >-- > >http://gbenson.net/ > Index: include/llvm/IntrinsicsPowerPC.td > =================================================================== > --- include/llvm/IntrinsicsPowerPC.td (revision 54985) > +++ include/llvm/IntrinsicsPowerPC.td (working copy) > @@ -26,6 +26,9 @@ > def int_ppc_dcbtst: Intri...

...be generated). What I need to know is, is the native code generated by LLVM relocatable such that it could be copied to another location in memory like this? Also, does LLVM do anything to the native code after it is first emitted? Does it try rewriting it, for example? Cheers, Gary -- http://gbenson.net/

Hi all, When I've been disassembling JIT-compiled functions I've noticed they all have the same three random instructions after them: bns- cr5,0xd04bbfe8 stfs f10,-16404(r3) stfs f10,-16404(r3) Is this meant to be there? Cheers, Gary -- http://gbenson.net/

...Cheng wrote: >> This does not patch cleanly for me (PPCISelLowering.cpp). Can you >> prepare a updated patch? > > This should work, though I won't have access to my test box now until > next Thursday so no guarantees :) > > Cheers, > Gary > > -- > http://gbenson.net/ > <ppc-atomics- > take4.patch>_______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

...out a SoC 2008 on Java, >> but I didn't find anything regarding its current state and documentation. > LLVM-Java has been rendered obsolete by http://vmkit.llvm.org/ so look into using VMKit instead. Also, if you can make the capability generic enough to use in Shark (more at http://gbenson.net/) that would be very useful. The key, I suspect, is to allow the Java front end mark an array.length field in such a way that LLVM knows that field doesn't alias anything else and is constant, so it can be hoisted out of loops. Andrew.

On Thu, Aug 20, 2009 at 6:42 AM, Gary Benson<gbenson at redhat.com> wrote: > Hi all, > > As I understand it, LLVM's JIT memory manager works by allocating a > 16Mb block of memory and generating native code into it.  Once that > block is exhausted no more functions can be JIT compiled.  I'm trying > to figure out ways to...

Hi all, I'm getting a weird error if I run llc on the attached module. Did I do something wrong (llc says the module is broken, also attached) or is this a bug? Cheers, Gary -- http://gbenson.net/ -------------- next part -------------- A non-text attachment was scrubbed... Name: test.bc Type: application/octet-stream Size: 2060 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20080617/dc2fc531/attachment.obj> -------------- next part ----------...

...nks for that. Attached is a working implementation of >>> llvm.memory.barrier. >>> >>>> Thanks for doing this btw. >>> >>> No problem, I need it! ;) >>> >>> Cheers, >>> Gary >>> >>> -- >>> http://gbenson.net/ > >> Index: include/llvm/IntrinsicsPowerPC.td >> =================================================================== >> --- include/llvm/IntrinsicsPowerPC.td (revision 54985) >> +++ include/llvm/IntrinsicsPowerPC.td (working copy) >> @@ -26,6 +26,9 @@ >>...

...ve forgotten why this is, there's a setting > somewhere. If you change the i8's in membarrier to i32's it > works. Thanks for that. Attached is a working implementation of llvm.memory.barrier. > Thanks for doing this btw. No problem, I need it! ;) Cheers, Gary -- http://gbenson.net/ -------------- next part -------------- Index: include/llvm/IntrinsicsPowerPC.td =================================================================== --- include/llvm/IntrinsicsPowerPC.td (revision 54985) +++ include/llvm/IntrinsicsPowerPC.td (working copy) @@ -26,6 +26,9 @@ def int_ppc_dcbt...

...If you change the i8's in membarrier to i32's it >> works. > > Thanks for that. Attached is a working implementation of > llvm.memory.barrier. > >> Thanks for doing this btw. > > No problem, I need it! ;) > > Cheers, > Gary > > -- > http://gbenson.net/ -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: memory-barrier-take2.patch URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20080821/6b36a0ee/attachment.ksh> -------------- next part -------------- > ____________________...

...In LLVM there is code to do this for function stubs on Macintosh, but not for other platforms and not for JITted code generally. The attached patch adds support for GNU platforms, but I can't figure out a nice way to call it for all generated code. Can anyone help? Cheers, Gary -- http://gbenson.net/ -------------- next part -------------- --- lib/Target/PowerPC/PPCJITInfo.cpp.orig 2008-06-11 07:12:39 +++ lib/Target/PowerPC/PPCJITInfo.cpp 2008-06-16 08:42:25 @@ -336,6 +336,20 @@ #if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \ defined(__APPLE__) sys_icac...

...(also attached) with llc I get the error "Cannot yet select: 0x10fa4ad0: ch = MemBarrier 0x10fa4828, 0x10fa4c68, 0x10fa4be0, 0x10fa4be0, 0x10fa4be0, 0x10fa4be0". This presumably means my "membarrier" pattern isn't being found... but why? Thanks in advance, Gary -- http://gbenson.net/ -------------- next part -------------- Index: include/llvm/IntrinsicsPowerPC.td =================================================================== --- include/llvm/IntrinsicsPowerPC.td (revision 54985) +++ include/llvm/IntrinsicsPowerPC.td (working copy) @@ -26,6 +26,9 @@ def int_ppc_dcbt...

...do contact Chris > about write access. > > On Aug 22, 2008, at 12:38 AMPDT, Gary Benson wrote: > > No, I don't. > > > > Cheers, > > Gary > > > > Dale Johannesen wrote: > > > This looks OK to check in, do you have write access? -- http://gbenson.net/

...going to the same destination, then if that destination contains phis you need to add the incoming value an equivalent number of times. The attached code seems wrong, but it compiles as correct, and removing the duplicated incoming node causes an error. Is this expected? Cheers, Gary -- http://gbenson.net/ -------------- next part -------------- define internal i32 @func419(i32* %foo_addr, i32* %bar_addr, i32 %baz) { %method = load i32* %foo_addr br label %not_zero not_zero: switch i32 %baz, label %no_exception9 [ i32 6, label %bci_56 i32...

Hi Andrew, Andrew Haley wrote: > Also, if you can make the capability generic enough to use in Shark > (more at http://gbenson.net/) that would be very useful. > > Agree. > The key, I suspect, is to allow the Java front end mark an array.length > field in such a way that LLVM knows that field doesn't alias anything else > and is constant, so it can be hoisted out of loops. > For that matter,...

...assembling JIT-compiled functions I've noticed they > all have the same three random instructions after them: > > bns- cr5,0xd04bbfe8 > stfs f10,-16404(r3) > stfs f10,-16404(r3) > > Is this meant to be there? > > Cheers, > Gary > > -- > http://gbenson.net/ > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev

...d they >> all have the same three random instructions after them: >> >> bns- cr5,0xd04bbfe8 >> stfs f10,-16404(r3) >> stfs f10,-16404(r3) >> >> Is this meant to be there? >> >> Cheers, >> Gary >> >> -- >> http://gbenson.net/ >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > _______________________________________________ > LLVM Develope...