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...th to handle multiplle latencies for same Read... Anyway as you reminded, I am searching for more Target and am looking into Pierre's change (I finally notice that he has a patch associated within the thread already :-) If it is feasible, I will try to make any suitable change back upstream) -Garfee On Sat, Nov 17, 2018, 10:42 AM Andrew Trick <atrick at apple.com wrote: > > > On Nov 16, 2018, at 6:31 PM, Garfee Guan <garfee.guan at gmail.com> wrote: > > Thanks Andrew. I have tried with recent tblgen, ReadAdvance would not work > for multiple latencies. Maybe I shou...

...ay have different latencies, depending both on the register reader and writer. I am freshman into tblgen. So I wonder if any other Target already has other way to describe that . On Fri, Nov 16, 2018, 8:00 AM Andrew Trick <atrick at apple.com wrote: > > > On Nov 14, 2018, at 10:52 PM, Garfee Guan via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi list, > I happened to read below thread (written in 3 years ago). I think I may > need this ReadAdvance feature to work with my ARCH. > > It is about the scheduler info which describes reading my ARCH's v...

...cycle count with ReadAdvance, or there is any existed method to meet my requirement. Anyway the latencies here seems to be decided by considering both a) 3 kinds of Write, b) 2 kinds of Read. Therefore I doubt if it can not be modeled with current tblgen implement. Can you comment and help? -- Garfee Guan, LLVM Compiler Backend Engineer Enflame Technology Co. Website: http://www.enflame-tech.com/ -------------------------------------------------------------------- [llvm-dev] Per-write cycle count with ReadAdvance *Pierre-Andre Saulais via llvm-dev* llvm-dev at lists.llvm.org <llvm-dev%40lis...