search for: g_ror

...essible using an unsigned 8-bit immediate rotated by an even number of bits %0 # I.e. just a plain vreg %0 = G_CONSTANT iN ${imm} # Where imm is 1 to 32 %2 = G_[AL]SHR %1, %0 %0 = G_CONSTANT iN ${imm} # Where imm is 0 to 31 %2 = G_SHL %1, %0 %0 = G_CONSTANT iN ${imm} # Where imm is 1 to 31 %2 = G_ROR %1, %0 # We don't actually have a rotate right at the moment so this would have to match the equivalent and/shift/or sequence %0 = G_CONSTANT iN 1 %2 = G_ROR %1, %0 # We don't actually have a rotate right at the moment so this would have to match the equivalent and/shift/or sequence %3 = G...

Thanks Nicolai! > On Nov 9, 2018, at 02:55, Nicolai Hähnle <nhaehnle at gmail.com> wrote: > > Hi Daniel, > > Lots of good stuff in there! I especially like the design for specifying out-of-line predicates. I have a couple of small comments and one major one below. > > > On 09.11.18 02:42, Daniel Sanders via llvm-dev wrote: >> _Passing arbitrary data from