search for: g_icmp

...and also possible combining of instructions and artifacts in pre/post legalizer combiner or elsewhere (e.g. in some sort of instruction-select patterns). I look at legality as "If generic instruction can be selected into machine instruction, it is legal". For example, let's look at G_ICMP and G_SELECT. In llvm IR type of result of icmp is always i1, and test argument (type 1) in select is also i1. Here is an .ll example: define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d) { entry:   %cmp = icmp slt i32 %a, %b   %cond = select i1 %cmp, i32 %d, i32 %c   ret i32 %cond } and corresponding M...

...if we have:   getActionDefinitionsBuilder(G_SELECT)       .legalFor({{s32, s32}, {s64, s32}, {p0, s32}})       .clampScalar(0, s32, s64)       .clampScalar(1, s32, s32)       .widenScalarToNextPow2(0); And in this case sizes of LLTs and register classes would be the same. Implementation for G_ICMP on AArch64 is very similar to second described option for G_SELECT. Is there a reason for different implementation of G_SELECT and G_ICMP on AArch64? Are there some general ruses to determine which of the two given options is better in which case? -------------- next part -------------- An HTML...

Hi, Mips32 has 64 bit floating point instructions, while i64 instructions have to be emulated with i32 instructions. This means that G_LOAD should be custom legalized for s64 integer value, and be legal for s64 floating point value. There are also other generic instructions with the same problem: G_STORE, G_SELECT, G_EXTRACT, and G_INSERT. There are also other configurations where integer

Hi Quentin, thank you for the reply! I have a couple more questions that came up when I tried to implement this today. I hope you can help me out with this again! Am 09.03.20 um 23:31 schrieb Quentin Colombet: > I would expect that you could create a register class and register > bank for the special register. That way you have something to map to > when you do register bank select.