search for: g92

Displaying 20 results from an estimated 56 matches for "g92".

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2016 Nov 19
3
[PATCH 0/2] Enable changing PCIe link on G92
one rename and one enable patch. Tested on hardware and confirmed with traces Karol Herbst (2): pci: Rename g94 to g92 pci/g92: Enable changing pcie link speeds drm/nouveau/include/nvkm/subdev/pci.h | 2 +- drm/nouveau/nvkm/engine/device/base.c | 22 +++++++++++----------- drm/nouveau/nvkm/subdev/pci/Kbuild | 2 +- drm/nouveau/nvkm/subdev/pci/{g94.c => g92.c} | 10 +++++----- drm/no...
2017 Feb 11
0
[PATCH] pci/g92: Fix rearm
704a6c008b7942bb7f30bb43d2a6bcad7f543662 broke pci msi rearm for g92 GPUs. g92 needs the nv46_pci_msi_rearm, where g94+ gpus used nv40_pci_msi_rearm. Reported-by: Andrew Randrianasulu <randrianasulu at gmail.com> Signed-off-by: Karol Herbst <karolherbst at gmail.com> --- drm/nouveau/include/nvkm/subdev/pci.h | 1 + drm/nouveau/nvkm/engine/device/base...
2017 Oct 01
0
[PATCH] bsp/g92: disable by default
G92's seem to require some additional bit of initialization before the BSP engine can work. It feels like clocks are not set up for the underlying VLD engine, which means that all commands submitted to the xtensa chip end up hanging. VP seems to work fine though. This still allows people to force-...
2019 Sep 17
1
[PATCH 1/3] pci: force disable ASPM before changing the link speed
On Fri, 13 Sep 2019 at 05:00, Karol Herbst <kherbst at redhat.com> wrote: > > taken from nvgpu > > Signed-off-by: Karol Herbst <kherbst at redhat.com> > --- > drm/nouveau/nvkm/subdev/pci/g84.c | 9 +++++++++ > drm/nouveau/nvkm/subdev/pci/g92.c | 1 + > drm/nouveau/nvkm/subdev/pci/g94.c | 1 + > drm/nouveau/nvkm/subdev/pci/gf100.c | 1 + > drm/nouveau/nvkm/subdev/pci/gf106.c | 1 + > drm/nouveau/nvkm/subdev/pci/gk104.c | 1 + > drm/nouveau/nvkm/subdev/pci/pcie.c | 14 ++++++++++++++ > drm/nouveau/nvkm/subdev/...
2019 Sep 12
5
[PATCH 0/3] PCIe link change improvements
...ng our infamous runpm issues on recent laptops Karol Herbst (3): pci: force disable ASPM before changing the link speed pci/gk104: enable dl_mgr safe mode pci/gk104: wait for ltssm idle before changing the link drm/nouveau/nvkm/subdev/pci/g84.c | 9 +++++++++ drm/nouveau/nvkm/subdev/pci/g92.c | 1 + drm/nouveau/nvkm/subdev/pci/g94.c | 1 + drm/nouveau/nvkm/subdev/pci/gf100.c | 1 + drm/nouveau/nvkm/subdev/pci/gf106.c | 1 + drm/nouveau/nvkm/subdev/pci/gk104.c | 11 +++++++++++ drm/nouveau/nvkm/subdev/pci/pcie.c | 14 ++++++++++++++ drm/nouveau/nvkm/subdev/pci/priv.h | 2 ++...
2014 Nov 27
2
[Bug 86794] New: Several nouveau related errors with xf86-video-nouveau with NVIDIA G92 [GeForce 9800 GT] and GF108 [GeForce GT 620] (rev a1).
https://bugs.freedesktop.org/show_bug.cgi?id=86794 Bug ID: 86794 Summary: Several nouveau related errors with xf86-video-nouveau with NVIDIA G92 [GeForce 9800 GT] and GF108 [GeForce GT 620] (rev a1). Product: xorg Version: unspecified Hardware: Other OS: All Status: NEW Severity: normal Priority: medium Component: Driver/nouveau...
2019 Sep 12
0
[PATCH 1/3] pci: force disable ASPM before changing the link speed
taken from nvgpu Signed-off-by: Karol Herbst <kherbst at redhat.com> --- drm/nouveau/nvkm/subdev/pci/g84.c | 9 +++++++++ drm/nouveau/nvkm/subdev/pci/g92.c | 1 + drm/nouveau/nvkm/subdev/pci/g94.c | 1 + drm/nouveau/nvkm/subdev/pci/gf100.c | 1 + drm/nouveau/nvkm/subdev/pci/gf106.c | 1 + drm/nouveau/nvkm/subdev/pci/gk104.c | 1 + drm/nouveau/nvkm/subdev/pci/pcie.c | 14 ++++++++++++++ drm/nouveau/nvkm/subdev/pci/priv.h | 2 ++ 8 files c...
2017 Nov 18
1
Blank console but X11 works on MCP79 - old regression since 3.8
...> libdrm/tests. Not sure if it supports C8 though =/ It didn't. But it does now - I mailed a patch to dri-devel, also (with slight fix) available at https://people.freedesktop.org/~imirkin/patches/0001-modetest-add-C8-support-to-generate-SMPTE-pattern.patch This works on GK208 but not on G92 (whose display unit is much closer to your MCP79's). You can run as ./modetest -s DVI-I-1:1920x1200 at C8 This should display a SMPTE pattern, and exit when you hit enter. When it does so, it doesn't restore fbcon, but you can swtich to another vty to get console back. I get a white pict...
2015 Jun 25
2
What are the restrictions around loading indirect constbuf values
..._SM12)" /*0000*/ FADD R2, R2, -c[0x0][A1+0x0]; /* 0x08000780b5000409 */ /*0008*/ FADD R3, R3, -c[0x0][A1+0x1]; /* 0x08004780b500060d */ don't appear to execute properly. However just MOV'ing the values into registers works fine. This was observed on a G92 chip. See bug https://bugs.freedesktop.org/show_bug.cgi?id=91056. I was hoping you could save me some time and let me know what instructions can load things like c0[$a1+4] (or maybe it's only in combination with the modifier?), and which Tesla-family GPU's have those restrictions. Thanks,...
2018 Mar 07
1
TLD instruction usage in non-linked sampler mode
Hi Andy, Thanks for checking! I do see an issue on Tesla as well (at least G92, and I believe someone else reported on a GT215 or GT218). However I haven't confirmed that it's the identical issue to what I see on Fermi with quite as much certainty as what I've checked on a GF108. (For the G92, the texture buffer object test fails in the same way it does on Fermi,...
2014 Sep 08
1
[PATCH] gpio: rename g92 class to g94
...ines, while nv94 and later has 32. Accessing 0xe0c{0,4} registers on nv92 can lead to incorrect PDISP setup. This is a regression introduced with commit 9d0f5ec9ee0fd5dc5fc1cc2cf559286431e406e3 Author: Ben Skeggs <bskeggs at redhat.com> Date: Mon May 12 15:22:42 2014 +1000 gpio: split g92 class from nv50 Reported-by: estece on #nouveau Cc: stable at vger.kernel.org # 3.16+ Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com> --- nvkm/engine/device/nv50.c | 22 ++++++------- nvkm/engine/device/nvc0.c | 14 ++++----- nvkm/subdev/gpio/Makefile.am | 2 +- nvkm/subdev...
2003 Nov 19
0
Windows Offline Folders
...I"B @57-E<B!N86UE.B!N;V)O9'D)4F5A;"!N M86UE.B!.;V)O9'D*6S(P,#,O,3$O,3D@,C Z,30Z,#0L(#-=('-M8F0O<')O M8V5S<RYC.F-H86EN7W)E<&QY*#$P,C,I"B @0VAA:6YE9"!M97-S86=E"ELR M,# S+S$Q+S$Y(#(P.C$T.C T+" S72!S;6)D+W!R;V-E<W,N8SIS=VET8VA? M;65S<V%G92@V.#4I"B @<W=I=&-H(&UE<W-A9V4@4TU"=&-O;E@@*'!I9" R M.3,W,RD*6S(P,#,O,3$O,3D@,C Z,30Z,#0L(#-=('-M8F0O<V5C7V-T>"YC M.G-E=%]S96-?8W1X*#,R.2D*("!S971T:6YG('-E8R!C='@@*# L(# I("T@ M<V5C7V-T>%]S=&%C:U]N9'@@/2 P"ELR,#...
2019 Sep 17
6
[PATCH 0/6] Add workaround for fixing runpm
...vkm/core/device.h | 2 ++ drm/nouveau/include/nvkm/subdev/pci.h | 3 +- drm/nouveau/nouveau_drm.c | 6 ++++ drm/nouveau/nvkm/subdev/clk/base.c | 2 +- drm/nouveau/nvkm/subdev/pci/base.c | 2 ++ drm/nouveau/nvkm/subdev/pci/g84.c | 8 +++++ drm/nouveau/nvkm/subdev/pci/g92.c | 1 + drm/nouveau/nvkm/subdev/pci/g94.c | 1 + drm/nouveau/nvkm/subdev/pci/gf100.c | 1 + drm/nouveau/nvkm/subdev/pci/gf106.c | 1 + drm/nouveau/nvkm/subdev/pci/gk104.c | 29 +++++++++++++----- drm/nouveau/nvkm/subdev/pci/gp100.c | 11 +++++++ drm/nouveau/nvkm/subdev/pc...
2013 Oct 24
2
known MSI errata?
On Fri, Oct 25, 2013 at 7:43 AM, Robert Morell <rmorell at nvidia.com> wrote: > On Mon, Sep 30, 2013 at 10:44:12AM -0700, Lucas Stach wrote: >> Hi, >> >> recently we tried to enable MSI interrupts with nouveau. Unfortunately >> there have been some reports of things failing with certain cards, where >> it isn't entirely clear if this is a GPU errata or
2013 May 29
1
hardware donation (GeForce 6600 & GTS250)
hello nouveau devs! I have two nvidia cards lying around that are no longer in use: * Nvidia GeForce GTS250 E-Green, 512MB GDDR3 (NV92/G92 - NV50 family) * Nvidia GeForce 6600, 256MB (NV43 - NV40 family) They both are already well supported by the nouveau driver as far as I can tell. But if any dev can make use of them, please let me know, I would gladly donate them. Patrick
2012 Jun 04
1
Dual NVidia cards, dual monitors
...;t help. Just to test the obvious, I switched the DVI cables coming out of the two video cards and as you'd expect what shows in the two monitors is also switched. When I do an lspci at the command line I see at the bottom of the listing: 60:00.0 VGA compatible controller: nVidia Corporation G92 [GeForce 8800 GT] (rev a2) 80:00.0 VGA compatible controller: nVidia Corporation G92 [GeForce 8800 GT] (rev a2) And the output from xrandr is: Screen 0: minimum 320 x 200, current 2560 x 1600, maximum 8192 x 8192 DVI-I-3 connected 2560x1600+0+0 (normal left inverted right x axis y axis) 646mm x 4...
2006 Feb 24
3
Sorting alphanumerically
I'm trying to sort a DATAFRAME by a column "ID" that contains alphanumeric data. Specifically,"ID" contains integers all preceeded by the character "g" as in: g1, g6, g3, g19, g100, g2, g39 I am using the following code: DATAFRAME=DATAFRAME[order(DATAFRAME1$ID),] and was hoping it would sort the dataframe by ID in the following manner g1, g2, g3, g6, g19,
2010 Jul 15
1
Error using the mi package
...f3a* f3b* f3c* f3d* f3e* f4* f6* f7* f8* f9* f12* f14* f15* f16* f20* f21* f22* f23* f25* g2* g3* g6* g8* g9* g12* g13* g15* g17* g18* g22* g25* g26* g27* g28* g31* g34* g43* g55* g58* g59* g60* g61* g63* g65* g68a* g68b* g69* g70* g71* g91* g92* g93* g94* g95* Error in AveVar[s, i, ] <- c(avevar.mean, avevar.sd) : number of items to replace is not a multiple of replacement length And here is what traceback() gives: > traceback() 3: .local(object, ...) 2: mi(imp.data, info = info2, n.iter = 6, preprocess = FALSE) 1: mi(imp.da...
2018 Mar 02
2
TLD instruction usage in non-linked sampler mode
Hello, This question is in the context of Tesla / Fermi generations, which have explicit bindings for textures / samplers. It might also apply to Kepler+, not quite as sure due to the bindless nature. I've been trying to understand how the TLD operation works (which is used to implement texelFetch in GLSL). It does not appear to the op takes an explicit sampler id at all (unlike all the
2017 Nov 17
3
Blank console but X11 works on MCP79 - old regression since 3.8
On Friday 17 November 2017 18:41:17 Ilia Mirkin wrote: > On Fri, Nov 17, 2017 at 12:33 PM, Ondrej Zary > > <linux at rainbow-software.org> wrote: > > @@ -483,8 +483,8 @@ > > nouveau 0000:02:00.0: disp: 0860: 00000000 -> 00000500 > > nouveau 0000:02:00.0: disp: 0864: 00000000 > > nouveau 0000:02:00.0: disp: 0868: 00000000 -> 04000500 >