Displaying 6 results from an estimated 6 matches for "g8rc_with_sub_32".
2012 Sep 20
2
[LLVMdev] Scheduling question (memory dependency)
...********** MACHINEINSTRS **********
# Machine code for function _Z5check3foos: Post SSA
Frame Objects:
fi#-1: size=2, align=2, fixed, at location [SP+50]
Function Live Ins: %X3 in %vreg1, %X4 in %vreg2
0B BB#0: derived from LLVM BB %entry
Live Ins: %X3 %X4
16B %vreg2<def> = COPY %X4; G8RC_with_sub_32:%vreg2
32B %vreg1<def> = COPY %X3; G8RC:%vreg1
48B STH8 %vreg1<kill>, 0, <fi#-1>; mem:ST2[FixedStack-1] G8RC:%vreg1
64B %vreg4<def> = LHA 0, <fi#-1>; mem:LD2[%0] GPRC:%vreg4
...
---------------------------------------------------------------
So far,...
2012 Sep 21
0
[LLVMdev] Scheduling question (memory dependency)
...--------------------------------
One notable difference is the "!tbaa !0" decoration on the load. I
don't know whether this helps or not. Later the lowered instructions
look like:
------------------------------------------------------------------
16B %vreg2<def> = COPY %X4; G8RC_with_sub_32:%vreg2
32B %vreg1<def> = COPY %X3; G8RC:%vreg1
48B STH8 %vreg1<kill>, 0, <fi#-1>; mem:ST2[FixedStack-1] G8RC:%vreg1
64B %vreg0<def> = LHZ 0, <fi#-1>; mem:LD2[%i11] GPRC:%vreg0
...
------------------------------------------------------------------
No...
2012 Sep 21
2
[LLVMdev] Scheduling question (memory dependency)
...t;
> One notable difference is the "!tbaa !0" decoration on the load. I
> don't know whether this helps or not. Later the lowered instructions
> look like:
>
> ------------------------------------------------------------------
> 16B %vreg2<def> = COPY %X4; G8RC_with_sub_32:%vreg2
> 32B %vreg1<def> = COPY %X3; G8RC:%vreg1
> 48B STH8 %vreg1<kill>, 0, <fi#-1>; mem:ST2[FixedStack-1]
> G8RC:%vreg1
> 64B %vreg0<def> = LHZ 0, <fi#-1>; mem:LD2[%i11] GPRC:%vreg0
> ...
> ----------------------------------------...
2012 Sep 21
2
[LLVMdev] Scheduling question (memory dependency)
...!0" decoration on the load. I
> > > don't know whether this helps or not. Later the lowered instructions
> > > look like:
> > >
> > > ------------------------------------------------------------------
> > > 16B %vreg2<def> = COPY %X4; G8RC_with_sub_32:%vreg2
> > > 32B %vreg1<def> = COPY %X3; G8RC:%vreg1
> > > 48B STH8 %vreg1<kill>, 0, <fi#-1>; mem:ST2[FixedStack-1]
> > > G8RC:%vreg1
> > > 64B %vreg0<def> = LHZ 0, <fi#-1>; mem:LD2[%i11] GPRC:%vreg0
> > >...
2012 Sep 21
0
[LLVMdev] Scheduling question (memory dependency)
...erence is the "!tbaa !0" decoration on the load. I
> > don't know whether this helps or not. Later the lowered instructions
> > look like:
> >
> > ------------------------------------------------------------------
> > 16B %vreg2<def> = COPY %X4; G8RC_with_sub_32:%vreg2
> > 32B %vreg1<def> = COPY %X3; G8RC:%vreg1
> > 48B STH8 %vreg1<kill>, 0, <fi#-1>; mem:ST2[FixedStack-1]
> > G8RC:%vreg1
> > 64B %vreg0<def> = LHZ 0, <fi#-1>; mem:LD2[%i11] GPRC:%vreg0
> > ...
> > ----------...
2012 Sep 21
0
[LLVMdev] Scheduling question (memory dependency)
...he load. I
> > > > don't know whether this helps or not. Later the lowered instructions
> > > > look like:
> > > >
> > > > ------------------------------------------------------------------
> > > > 16B %vreg2<def> = COPY %X4; G8RC_with_sub_32:%vreg2
> > > > 32B %vreg1<def> = COPY %X3; G8RC:%vreg1
> > > > 48B STH8 %vreg1<kill>, 0, <fi#-1>; mem:ST2[FixedStack-1]
> > > > G8RC:%vreg1
> > > > 64B %vreg0<def> = LHZ 0, <fi#-1>; mem:LD2[%i11] GPRC:%vreg0
> >...