Displaying 5 results from an estimated 5 matches for "g8rc_and_g8rc_nox0".
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...t of the function. Those loads use 12
registers before any of the divides are scheduled. As a result, we end up
with significantly higher register pressure after all the loads.
--
0B BB#0: derived from LLVM BB %entry
Live Ins: %X3 %X4
16B %vreg1<def> = COPY %X4; G8RC_and_G8RC_NOX0:%vreg1
32B %vreg0<def> = COPY %X3; G8RC_and_G8RC_NOX0:%vreg0
48B %vreg2<def> = LD 0, %vreg0; mem:LD8[%num](tbaa=!4)
G8RC:%vreg2 G8RC_and_G8RC_NOX0:%vreg0
64B %vreg3<def> = LD 0, %vreg1; mem:LD8[%den](tbaa=!4)
G8RC:%vreg3 G8RC_and_G8RC_NOX0:%vr...
2017 Oct 13
3
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...12 registers before any of the divides are scheduled. As a result, we end up with significantly higher register pressure after all the loads.
>> --
>> 0B BB#0: derived from LLVM BB %entry
>> Live Ins: %X3 %X4
>> 16B %vreg1<def> = COPY %X4; G8RC_and_G8RC_NOX0:%vreg1
>> 32B %vreg0<def> = COPY %X3; G8RC_and_G8RC_NOX0:%vreg0
>> 48B %vreg2<def> = LD 0, %vreg0; mem:LD8[%num](tbaa=!4) G8RC:%vreg2 G8RC_and_G8RC_NOX0:%vreg0
>> 64B %vreg3<def> = LD 0, %vreg1; mem:LD8[%den](tbaa=!4) G8RC:%vre...
2017 Feb 09
2
Improving the split heuristics for the Greedy Register Allocator
...t; 10 Predecessors according to CFG: BB#0
> 11 B <BB#3>
> 12 Successors according to CFG: BB#3(?%)
> 13
> 14 BB#1: derived from LLVM BB %if.end
> 15 Predecessors according to CFG: BB#0
> 16 %vreg6<def> = ADDIStocHA %X2, <ga:@a>; G8RC_and_G8RC_NOX0:%vreg6
> 17 %vreg7<def> = LDtocL <ga:@a>, %vreg6, %X2<imp-use>;
> mem:LD8[GOT] G8RC_and_G8RC_NOX0:%vreg7,%vreg6
> 18 %vreg8<def> = LWA 0, %vreg7;
> mem:LD4[@a](tbaa=!3)(dereferenceable) G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg7
> 19 %vre...
2017 Jan 13
2
Improving the split heuristics for the Greedy Register Allocator
...80000000 = 62.50%)
8
9 BB#4:
10 Predecessors according to CFG: BB#0
11 B <BB#3>
12 Successors according to CFG: BB#3(?%)
13
14 BB#1: derived from LLVM BB %if.end
15 Predecessors according to CFG: BB#0
16 %vreg6<def> = ADDIStocHA %X2, <ga:@a>; G8RC_and_G8RC_NOX0:%vreg6
17 %vreg7<def> = LDtocL <ga:@a>, %vreg6, %X2<imp-use>;
mem:LD8[GOT] G8RC_and_G8RC_NOX0:%vreg7,%vreg6
18 %vreg8<def> = LWA 0, %vreg7;
mem:LD4[@a](tbaa=!3)(dereferenceable) G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg7
19 %vreg9<def> = CMPLD %vr...
2018 Dec 07
2
Should intrinsics llvm.eh.sjlj.setjmp be with isBarrier flag?
...fall-through but ends with a
barrier instruction! ***
function: main
basic block: %bb.2 for.body.lr.ph (0x100275437e8)
Content in block BB.2:
BB#2: derived from LLVM BB %for.end
Predecessors according to CFG: BB#1
%vreg2<def> = ADDIStocHA %X2, <ga:@env_sigill>;
G8RC_and_G8RC_NOX0:%vreg2
%vreg3<def> = LDtocL <ga:@env_sigill>, %vreg2<kill>; mem:LD8[GOT]
G8RC:%vreg3 G8RC_and_G8RC_NOX0:%vreg2
%vreg4<def> = EH_SjLj_SetJmp64 %vreg3<kill>, %CTR8<imp-def,dead>;
GPRC:%vreg4 G8RC:%vreg3
Currently Powerpc sets EH_SjLj_SetJmp64 with...