search for: g84_pcie_version

...t; + u32 value = status ? 0x180 : 0x0; > + nvkm_pci_mask(pci, 0x150, 0x180, value); > +} > + > int > g84_pcie_init(struct nvkm_pci *pci) > { > @@ -147,6 +155,7 @@ g84_pci_func = { > .pcie.set_version = g84_pcie_set_version, > .pcie.version = g84_pcie_version, > .pcie.version_supported = g84_pcie_version_supported, > + .pcie.force_aspm_off = g84_pcie_force_aspm_off, > }; > > int > diff --git a/drm/nouveau/nvkm/subdev/pci/g92.c b/drm/nouveau/nvkm/subdev/pci/g92.c > index 48874359d..8c35cc89e 100644 > --- a/drm/nouv...

everything was taken from nvgpu. Main reason for adding is to improve stability of the PCIe link changing code as we might want to depend on it for a workaround fixing our infamous runpm issues on recent laptops Karol Herbst (3): pci: force disable ASPM before changing the link speed pci/gk104: enable dl_mgr safe mode pci/gk104: wait for ltssm idle before changing the link

...force_aspm_off(struct nvkm_pci *pci, bool status) +{ + /* L0s and L1 */ + u32 value = status ? 0x180 : 0x0; + nvkm_pci_mask(pci, 0x150, 0x180, value); +} + int g84_pcie_init(struct nvkm_pci *pci) { @@ -147,6 +155,7 @@ g84_pci_func = { .pcie.set_version = g84_pcie_set_version, .pcie.version = g84_pcie_version, .pcie.version_supported = g84_pcie_version_supported, + .pcie.force_aspm_off = g84_pcie_force_aspm_off, }; int diff --git a/drm/nouveau/nvkm/subdev/pci/g92.c b/drm/nouveau/nvkm/subdev/pci/g92.c index 48874359d..8c35cc89e 100644 --- a/drm/nouveau/nvkm/subdev/pci/g92.c +++ b/drm/nouveau/nvkm/s...

I merged the both series I sent out recently into one bigger one so that it's more obvious on why all of that is needed. Biggest changes since last sent: * reworked the ASPM patch * removed "pci: add nvkm_pcie_get_speed" patch Please test this on Laptops and report back if it either breaks something or doesn't fix runpm. Thanks Karol Herbst (6): pci: disable ASPM before

overall the same as the old stuff, but with better namings and tirivialy improved code here and there Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement generic code for PCIe speed change pci: implement pcie speed change for tesla pci: implement pcie speed change on Fermi pci: implement PCIe speed change for kepler+ bios/perf: parse the pci speed from the

overall it is for the most part the same as my older version. I cleaned up some copyright things, so that it is more like the others. Also I moved the print about the max speed supported into preinit and did some other minor cleanups in the 3rd commit. Happy testing (and performance for prime offloading setups) Karol Herbst (9): pci: add gk104 variant pci: add gf106 variant pci: implement

....wr08 = nv40_pci_wr08, + .wr32 = nv40_pci_wr32, + .msi_rearm = nv40_pci_msi_rearm, + + .pcie.init = g84_pcie_init, + .pcie.set_link = g84_pcie_set_link, + + .pcie.max_speed = g84_pcie_max_speed, + .pcie.cur_speed = g84_pcie_cur_speed, + + .pcie.set_version = g84_pcie_set_version, + .pcie.version = g84_pcie_version, + .pcie.version_supported = g92_pcie_version_supported, +}; + +int +g94_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +{ + return nvkm_pci_new_(&g94_pci_func, device, index, ppci); +} -- 2.11.1

one rename and one enable patch. Tested on hardware and confirmed with traces Karol Herbst (2): pci: Rename g94 to g92 pci/g92: Enable changing pcie link speeds drm/nouveau/include/nvkm/subdev/pci.h | 2 +- drm/nouveau/nvkm/engine/device/base.c | 22 +++++++++++----------- drm/nouveau/nvkm/subdev/pci/Kbuild | 2 +- drm/nouveau/nvkm/subdev/pci/{g94.c => g92.c} |

Changes since last sent: * add a patch to set the device into DRM_SWITCH_POWER_CHANGING state (can be dropped actually, I thought I was needing it, came up with a different approach and forgot to delete it, doesn't hurt though) * expose information about runtime suspending to nvkm so that we can run the pcie workaround only on runtime suspend Karol Herbst (8): pci: disable ASPM