Displaying 2 results from an estimated 2 matches for "fuse_reserved_calib0".
2016 Jun 07
0
[PATCH] clk/gm20b: fix build on non-tegra platforms
...au/nvkm/subdev/clk/gm20b.c
+++ b/drm/nouveau/nvkm/subdev/clk/gm20b.c
@@ -946,11 +946,13 @@ gm20b_clk_init_fused_params(struct gm20b_clk *clk)
{
struct nvkm_subdev *subdev = &clk->base.base.subdev;
u32 val;
- u32 rev;
+ u32 rev = 0;
+#if IS_ENABLED(CONFIG_ARCH_TEGRA)
tegra_fuse_readl(FUSE_RESERVED_CALIB0, &val);
rev = (val >> FUSE_RESERVED_CALIB0_FUSE_REV_SHIFT) &
MASK(FUSE_RESERVED_CALIB0_FUSE_REV_WIDTH);
+#endif
/* No fused parameters, we will calibrate later */
if (rev == 0)
--
2.8.3
2016 Jun 01
15
[PATCH 00/15] clk/tegra: improve code and add DFS support
This series adds support for GM20B PLL's Maxwell features, namely glitchless
switch and (more importantly) DFS support. DFS lets the PLL lower its output
speed according to input current variations, making the clock more stable and
allowing it to run safely at lower voltage.
All GM20B additions are done in the last patch, which consequently ends up
being considerably big ; fortunately, it