search for: fus

On Apr 2, 2008, at 1:14 AM, Pertti Kellomäki wrote: > I am pretty excited about the recent activity on dependence > analysis. The only remaining problem from our point of view > is how to get the alias information to the back end instruction > scheduler. If I understand things correctly, the alias information > basically gets lost in the process of lowering to target >

I am pretty excited about the recent activity on dependence analysis. The only remaining problem from our point of view is how to get the alias information to the back end instruction scheduler. If I understand things correctly, the alias information basically gets lost in the process of lowering to target instructions. We are interested in the DSP domain, so we really need to get SIMD style

Here is the code <https://github.com/llvm-mirror/llvm/blob/c68dcdb413079d92118839dbd835e125293f411a/include/llvm/MC/MCInstrItineraries.h#L75> for InstrStage::getUnits() /// \brief Returns the choice of FUs. unsigned getUnits() const { return Units_; } This method returns an integer. How does one interpret it? As far as I see it it should tell me what resources are used by a given stage but I can't figure out what a return value means. Would anyone care to help? Thanks, -- Rail Shafigulin Soft...

...alf Of *Jonas Paulsson *Sent:* Monday, February 11, 2013 11:16 AM *To:* llvmdev at cs.uiuc.edu *Subject:* [LLVMdev] DFAPacketizer Hi, I am having problems writing the ProcessorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise: InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, InstrStage<1, [ALU1, ALU2]>]> I want to express that there are two ALU's, and four bundle slots, and in this case while allocating this type of instructions se...

Hello, I want to implement vectorization and vliw(very long instruction word) in my specific dsp ,do you have any advices to me ? Thank you very much! -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170220/7bfe1d15/attachment.html>

...llvmdev at cs.uiuc.edu <mailto:llvmdev at cs.uiuc.edu> > *Subject:* [LLVMdev] DFAPacketizer > > Hi, > > I am having problems writing the ProcessorItineraries list. As > instructions on my VLIW target have varying size I want to model both > cpu units and bundle bits as FUs. The following does not work, to my > surprise: > > InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, > > InstrStage<1, [ALU1, ALU2]>]> > > I want to express that there are two ALU's, and four bundle slots, and > in this case while a...

...Monday, February 11, 2013 11:16 AM To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu> Subject: [LLVMdev] DFAPacketizer Hi, I am having problems writing the ProcessorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise: InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, InstrStage<1, [ALU1, ALU2]>]> I want to express that there are two ALU's, and four bundle slots, and in this case while allocating...

...Monday, February 11, 2013 11:16 AM To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu> Subject: [LLVMdev] DFAPacketizer Hi, I am having problems writing the ProcessorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise: InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, InstrStage<1, [ALU1, ALU2]>]> I want to express that there are two ALU's, and four bundle slots, and in this case while allocating...

Hi, I am having problems writing the ProcessorItineraries list. As instructions on my VLIW target have varying size I want to model both cpu units and bundle bits as FUs. The following does not work, to my surprise: InstrItinData<ALU, [InstrStage<1, [BITS1,BITS2, BITS3, BITS4], 0>, InstrStage<1, [ALU1, ALU2]>]> I want to express that there are two ALU's, and four bundle slots, and in this case while allocating...

...0 kkrenn (557366) Email: c.fuerstaller@kurtkrenn.com sip: c.fuerstaller@kurtkrenn.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.2 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFFyGDXR0exH8dhr/YRAgxxAKCsren0xCF4K+8yfLBpfF8BeCSFJwCeKzkh hoOSPICBGr9mEctSw19/fUs= =PM9C -----END PGP SIGNATURE-----

Hi I got wine from Sourceforge and extracted it to a folder. In that folder I open a terminal and want to check dependencies . I get this : fuz at Fuzzy:~/linux saved/wine-0.9.58$ ./configure checking build system type... i686-pc-linux-gnulibc1 checking host system type... i686-pc-linux-gnulibc1 checking whether make sets $(MAKE)... yes checking for gcc... gcc checking for C compiler default

We are using LLVM to target a customizable processor architecture. One of the activities to be supported is architecture exploration, where one explores the processor design space (e.g. connectivity, number of FUs) and tries to find a good match for the application at hand. The exploration needs to be relatively rapid, so targeting and compiling gcc for each of the processor variants is not feasible. My understanding at this point is that in order to make things work correctly, gcc needs to know about the...

...implemented with the state machine approach or just a resource table. VLIW scheduling requires also multiplicity for the FU resource constraints. Can those be described in the current TableGen format? Clustered (or in general, not-fully-connected) VLIWs also require connectivity information (which FUs are connected to which RFs) but that can be modeled with register classes, I've been told. -- --Pekka

...YQadaqfMkPIc5wCP8Ko69eXE8GoRSySpCh2g\r\ns/UA8Hn8K6nwrpscXhd5Vupfttw/mqFX 5WTqCD6DvxUSxdTeTM5YSFvdVhmueK/7Mguba8mkmuY/\r\nlAC580Zxn6CuP8GeLrq31oWOhotx cXzYkVlGVj7n0yMn9Kf4h0LXZ7o393p8U1o5UnbMPnVsDIz2\r\n9R1617R8H/BWl2vhnxDfXUcF rqYnVYJBuJxySB6ZwPzonKMlZkU4SjscV4puNW1a/nkvWZPscZij\r\nUqR5YI569WP+FeWx+FUs oY573fCzjIJbdux3OD1r3zWPEVpYmRbyyS6WJljjkcbizsOOnQ8155q3\r\nhnWdVkkQMbKKF1fa w+6vpj19q3o01y3RhiPi1J9H8KwavaKn2mFFGwGUEEkH3PGOD9K9bvrzwvpk\r\neu29rrs"..., 8192) = 8192 190074 write(8, "4SJuCeSNxH05pyfK+aO5hKKkrPY8n8TeBNH\r\ngvJ5LrV54YxgtG6Blkx0wfTIxWZ4Z1PU9R1a 7hs7YQadaqfMkPIc5wCP8Ko69eXE8...

...writeable = yes guest ok = no write list = @domadmins root administrator ----------------------------------- So, does any one have an idea how can I make this work? Thanks in advance, -- Daniel Gomes (SysAdmin) dgomes at ipfn.ist.utl.pt Ext. 3487 - 218419487 Instituto de Plasmas e Fus?o Nuclear Instituto Superior T?cnico - UTL Av. Rovisco Pais - 1049-001 Lisboa - Portugal

On Dec 2, 2011, at 12:40 PM, Evan Cheng wrote: > There have been quite a bit of discussions about adding machine instruction bundle to support VLIW targets. I have been pondering what the right representation should be and what kind of impact it might have on the LLVM code generator. I believe I have a fairly good plan now and would like to share with the LLVM community. Let me add some

...> can customize some things. It might very well come down to the same > decision to write our own pass that implements our own scheduler, and then > utilize ModuloSchedule and an Expander to make changes. One interesting > topic that came up was unrolling to get more utilization of the FUs. > Someone had already identified this optimization in > https://reviews.llvm.org/D53005, but it seems to have gone stale. I’m > also curious about customizing the expander, since we too have some ways to > make the prolog and epilog more efficient. > > > > My current soluti...

********************************************************************** Este email assim como os ficheiros que possa ter em anexo s?o confidenciais e para uso exclusivo da pessoa ou organiza??o para o qual foi enviado. Se recebeu este email por engano por favor notifique Redes@bnc.pt Esta nota confirma que esta mensagem foi verificada pelo MIMEsweeper n?o tendo sido encontrados virus.

...ev] Machinepipeliner interface. > shouldIgnoreForPipelining, actually not ignoring. > > > > As I mentioned before, > this API was introduced by James, mostly for his out-of-tree > implementations, > the in tree implementation NEVER implement it. > > If it is causing confusion, I think we have two choices: > 1. See whether James would like to upstream part of his code? Or any other > target that would like to use this can post a patch to use it. > 2. Remove this confusing API in tree. > > > Best, > > Jinsong Ji (纪金松), PhD. > > XL/LLVM on...

...%tUP)lt2Unf-~F*HlM*+;QM> zdcb}w{9?DK<f$(L9ycocQ>P$%vq4?>93mSzvw=H<MtL!HIUm|2d-DR(a$QK-ry+kt z!z$j5xW*0HN0~3)binCr7vXMc6>?C!et)4y9twTjL^$!lrm24ss_7<c<KSy3f9&L9 zE-)87-r&)xd^-JTHV(g-!mIve->rHE?mR+Z7k7i}iMTUFbk0jcqp$Ox5SzcS)y=XW zy`I6r#vOCe$C9fnBOB3b`<h8NQIMP`YMfs%fUs-RJ|keeOA!B2I1WKXKbh#6rBLGv zgx5BW7qd2t(K%849T_ggkVP!&;5Rj?T1%8`v=o4uH}3a at dDeA1tMV770>s2C$U8JF z!ggf*8&%zv)Z}t6U9iOtDyE8l(<nfcx8+b?MsE|wtL0cEr*zb;Q87 at SzBo@TnJ2+Y z%Eu3CUW<{20KinW3;p4McE`NzjTV{jEIIt2OLMZYFqnM74xm$=$C_5GYiT1Y8x3!w z5SQl3s5Tp+v|N&H_xF?E#fmA{PbOixW!HB;-JknB4HJ...