search for: funcunit

...stage to the start of // the next stage in the itinerary. For example: // // A stage is specified in one of two ways: // // InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles // InstrStage<1, [FU_x, FU_y], 0> - TimeInc explicit // class InstrStage<int cycles, list<FuncUnit> units, int timeinc = -1, ReservationKind kind = Required> { int Cycles = cycles; // length of stage in machine cycles list<FuncUnit> Units = units; // choice of functional units int TimeInc = timeinc; // cycles t...

...eserve the resources occupied by a MCInstrDesc and // change the current state to reflect that change. void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { unsigned InsnClass = MID->getSchedClass(); const llvm::InstrStage *IS = InstrItins->beginStage(InsnClass); unsigned FuncUnits = IS->getUnits(); UnsignPair StateTrans = UnsignPair(CurrentState, FuncUnits); ReadTable(CurrentState); assert(CachedTable.count(StateTrans) != 0); CurrentState = CachedTable[StateTrans]; } This happens at the packetization stage, i.e. scheduling seems to work. My schedule description...

> > It's hard to make a guess based on that assertion alone. Apparently there > is no transition in the DFA for these values. > > Do the arguments (e.g. CurrentState and FuncUnits) look reasonable? FuncUnits = 0 CurrentState = 0 StateTrans = {first = 0, second = 0} I understand that there is something wrong with the state machine but I can't figure out what exactly. My scheduler description is the same as for Hexagon or R600. So why would DFA would look any different...

...ficient. Too bad, Y-bundles can't contain arbitrary instructions. So, there are 5 virtual pipelines: X0, X1, Y0, Y1, Y2. I can define that which pipelines can be used to perform an instruction. On the other hand, AFAIK one subtarget can be matched only with one ProcessorItineraries and all its FuncUnits may be used in each bundle. Thus, I can't constraint bundles to use either X0, X1 or Y0, Y1, Y2, and never mix them. Is there a way to define two types of bundles using the current capabilities of TableGen and CodeGen? Or had I better use only X-bundles for now? Thanks for any suggestions, D...

...tructions can be, and which ones will move forward as the next > dispatched group, and I think we need to fallback into C++ to deal with > them. Right. I should have mentioned that the static itinerary really can't express dynamic constraints. You can play games by inventing new types of FuncUnits. But there's no way to say an instruction hogs a pipeline until some future event at unknown interval. -Andy

On Mon, 11 Jun 2012 10:48:18 -0700 Andrew Trick <atrick at apple.com> wrote: > On Jun 11, 2012, at 9:30 AM, Hal Finkel <hfinkel at anl.gov> wrote: > > > I'm considering writing more-detailed itineraries for some PowerPC > > CPUs that use the 'traditional' instruction grouping scheme. In > > essence, this means that multiple instructions will stall

...) continue; >> diff --git a/lib/Target/Hexagon/HexagonSchedule.td b/lib/Target/Hexagon/HexagonSchedule.td >> index fbea445..c488796 100644 >> --- a/lib/Target/Hexagon/HexagonSchedule.td >> +++ b/lib/Target/Hexagon/HexagonSchedule.td >> @@ -13,7 +13,6 @@ def LSUNIT : FuncUnit; >> def MUNIT : FuncUnit; >> def SUNIT : FuncUnit; >> >> - >> // Itinerary classes >> def ALU32 : InstrItinClass; >> def ALU64 : InstrItinClass; >> @@ -24,23 +23,25 @@ def LD : InstrItinClass; >> def M...

.../ > +// Target-independent interfaces which we are implementing > +//===----------------------------------------------------------------------===// > + > +include "llvm/Target/Target.td" > + > +// Dummy Instruction itineraries for pseudo instructions > +def ALU_NULL : FuncUnit; > +def NullALU : InstrItinClass; > + > +//===----------------------------------------------------------------------===// > +// AMDIL Subtarget features. > +//===----------------------------------------------------------------------===// > +def FeatureFP64 : SubtargetFeature&l...