Displaying 6 results from an estimated 6 matches for "funcletlayout".
2015 Dec 10
2
Allowing virtual registers after register allocation
...argetMachine is MachineCopyPropagation.
> Several passes (post-RA MachineLICM, StackSlotColoring) already only run if RA runs.
> Everything else is running today. Currently that's ShrinkWrap, BranchFolder, ExpandPostRAPseudos, PostRAScheduler, GCMachineCodeAnalysis, MachineBlockPlacement, FuncletLayout, and StackMapLiveness. All of these run after our register coloring pass.
I don’t know for the other passes, but I don’t think it makes sense to teach PrologEpilogInserter to work on virtual registers, since part of its job is to get rid of any virtual registers created when lowering the frame.
I....
2015 Dec 10
2
Allowing virtual registers after register allocation
> On Dec 10, 2015, at 9:39 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>
>
>
> ----- Original Message -----
>> From: "Quentin Colombet" <qcolombet at apple.com>
>> To: "Derek Schuff" <dschuff at google.com>
>> Cc: "Hal Finkel" <hfinkel at anl.gov>, llvm-dev at lists.llvm.org
>> Sent: Wednesday, December
2016 Jan 13
2
Allowing virtual registers after register allocation
...hine late optimization:
BranchFolderPass
TailDuplicate
MachineCopyPropagation
PostRAScheduler
ExpandPostRAPseudos
ImplicitNullChecks (optional)
PostMachineScheduler or PostRAScheduler
GC:
GCMachineCodeAnalysis
GC info printer
Block Placement:
MachineBlockPlacement
MachineBlockPlacementStats
FuncletLayout
StackMapLiveness
LiveDebugValues
All of the pre-regalloc passes (and analyses) would just get marked as
supporting virtual registers.
Here are some notes about passes of interest:
PostRAMachineLICM (if not overriden by the target) is just the same
MachineLICM which runs before regalloc and so h...
2016 Jan 22
2
Allowing virtual registers after register allocation
...; MachineCopyPropagation
> PostRAScheduler
> ExpandPostRAPseudos
> ImplicitNullChecks (optional)
> PostMachineScheduler or PostRAScheduler
> GC:
> GCMachineCodeAnalysis
> GC info printer
> Block Placement:
> MachineBlockPlacement
> MachineBlockPlacementStats
> FuncletLayout
> StackMapLiveness
> LiveDebugValues
>
> All of the pre-regalloc passes (and analyses) would just get marked as
> supporting virtual registers.
>
>
> Here are some notes about passes of interest:
>
> PostRAMachineLICM (if not overriden by the target) is just the same
&...
2016 Jan 22
2
Allowing virtual registers after register allocation
...>>> ImplicitNullChecks (optional)
>>> PostMachineScheduler or PostRAScheduler
>>> GC:
>>> GCMachineCodeAnalysis
>>> GC info printer
>>> Block Placement:
>>> MachineBlockPlacement
>>> MachineBlockPlacementStats
>>> FuncletLayout
>>> StackMapLiveness
>>> LiveDebugValues
>>>
>>> All of the pre-regalloc passes (and analyses) would just get marked as supporting virtual registers.
>>>
>>>
>>> Here are some notes about passes of interest:
>>>
>>>...
2015 Dec 10
3
Allowing virtual registers after register allocation
To say this first: This whole discussion about using virtregs until emit or having growable physregs is hard to argue without actually having experience trying to go either way.
Problems when using virtregs throughout the backend until emit time:
- The MC layer is using MCPhysReg (which is an uint16_t) and would need retrofitting to support virtregs
- VirtRegs are assumed to have a definition,