Displaying 2 results from an estimated 2 matches for "fullvec".
2018 Jun 15
2
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
...ication?
To split a <scalable 2 x double> in half, you'd use a shufflevector in much the
same way you would for fixed-length vector types.
e.g.
``
%sv = call <scalable 1 x i32> @llvm.experimental.vector.stepvector.nxv1i32()
%halfvec = shufflevector <scalable 2 x double> %fullvec, <scalable 2 x double> undef, <scalable 1 x i32> %sv
``
You can't split it any further than a <scalable 1 x <ty>>, since there may only be
one element in the actual hardware vector at runtime. The same restriction applies to
a <1 x <ty>>. This is why we have...
2018 Jun 05
14
[RFC][SVE] Supporting SIMD instruction sets with variable vector lengths
Hi,
Now that Sander has committed enough MC support for SVE, here's an updated
RFC for variable length vector support with a set of 14 patches (listed at the end)
to demonstrate code generation for SVE using the extensions proposed in the RFC.
I have some ideas about how to support RISC-V's upcoming extension alongside
SVE; I'll send an email with some additional comments on