search for: fsub64

Displaying 7 results from an estimated 7 matches for "fsub64".

2006 Oct 09
2
[LLVMdev] FP emulation
...-effects, they look pretty much like real instructions. Thus I have the idea to represent them in the tblgen instruction descriptions like pseudo-instructions, where constraints define which concrete physical %dX registers are to use. This would enfore correct register allocation. For example: def FSUB64: I<0x11, (ops), "fsub64", [(set d0, (fsub d0, d1))]>, Imp<[d0,d1],[d0,d1]>; // Uses d0, d1 and defines d0,d1 This seems to work, at least on simple test files. But I would also need a way to convert such a FSUB64 pseudo-instruction into the assembler...
2006 Oct 09
0
[LLVMdev] FP emulation
...ke real instructions. Thus I have the idea to > represent them in the tblgen instruction descriptions like > pseudo-instructions, where constraints define which concrete physical > %dX registers are to use. This would enfore correct register > allocation. > > For example: > def FSUB64: I<0x11, (ops), "fsub64", [(set d0, (fsub d0, d1))]>, > Imp<[d0,d1],[d0,d1]>; // Uses d0, d1 and defines d0,d1 > > This seems to work, at least on simple test files. That should be a robust solution. > But I would also need a way to convert such a FSUB6...
2006 Oct 09
0
[LLVMdev] tblgen multiclasses
Hi Chris, Thanks for this info. This provides even better and more advanced examples of multiclass usage! But your previous explanations were so good that I implemented in my backend last week almost the same that you've done now in the X86InstrSSE.td. I even introduced isCommutable parameter to indicate this property, just as you did. So, by now integer arithmetic and general purpose
2006 Oct 08
3
[LLVMdev] tblgen multiclasses
For anyone interested, X86InstrSSE.td makes extensive use of multiclasses now if people are looking for examples other than the sparc backend. -Chris -- http://nondot.org/sabre/ http://llvm.org/
2006 Oct 10
4
[LLVMdev] FP emulation
...ea to > > represent them in the tblgen instruction descriptions like > > pseudo-instructions, where constraints define which concrete > physical > > %dX registers are to use. This would enfore correct register > > allocation. > > > > For example: > > def FSUB64: I<0x11, (ops), "fsub64", [(set d0, (fsub d0, d1))]>, > > Imp<[d0,d1],[d0,d1]>; // Uses d0, d1 and defines d0,d1 > > > > This seems to work, at least on simple test files. > > That should be a robust solution. > > > But I would also...
2006 Oct 10
0
[LLVMdev] FP emulation
On Tue, 10 Oct 2006, Roman Levenstein wrote: >>> such a call instruction? >> >> Why not just make the asm string be "call __fsub64"? > > Well, of course it would be the best solution. But the interesting part > is that I need to generate the machine code directly because for > different reasons use of a system assembler is not an option. As a ok. > result, I need to do this conversion in the target backen...
2006 Oct 11
5
[LLVMdev] FP emulation
> On Tue, 10 Oct 2006, Roman Levenstein wrote: > >>> such a call instruction? > >> > >> Why not just make the asm string be "call __fsub64"? > > > > Well, of course it would be the best solution. But the interesting > part > > is that I need to generate the machine code directly because for > > different reasons use of a system assembler is not an option. As a > > ok. > > > result, I ne...