Displaying 9 results from an estimated 9 matches for "fsr8".
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fsr0
2008 Oct 18
2
[LLVMdev] INSERT_SUBREG node.
...arts using INSERT_SUBREG.
> >
> > The workaround is to declare the same SubRegClass twice while
> > declaring
> > the SuperRegisterClass. i.e.
> >
> > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> > let SubRegClassList = [FSR8, FSR8]; // HERE.
> > }
>
> This is a bug, probably in tablegen. Unfortunately I don't have the
> time to fix it. But please file a bug about this. Hopefully someone
> will fix it soon.
>
> Thanks,
>
> Evan
>
PR2916 filed.
Though I did not quite unders...
2008 Oct 20
2
[LLVMdev] INSERT_SUBREG node.
...workaround is to declare the same SubRegClass twice while
> > > > declaring
> > > > the SuperRegisterClass. i.e.
> > > >
> > > > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> > > > let SubRegClassList = [FSR8, FSR8]; // HERE.
> > > > }
> > >
> > > This is a bug, probably in tablegen. Unfortunately I don't have
> > > the
> > > time to fix it. But please file a bug about this. Hopefully
> > > someone
> > > will fix it soon.
>...
2008 Oct 20
0
[LLVMdev] INSERT_SUBREG node.
...SUBREG.
>>>
>>> The workaround is to declare the same SubRegClass twice while
>>> declaring
>>> the SuperRegisterClass. i.e.
>>>
>>> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
>>> let SubRegClassList = [FSR8, FSR8]; // HERE.
>>> }
>>
>> This is a bug, probably in tablegen. Unfortunately I don't have the
>> time to fix it. But please file a bug about this. Hopefully someone
>> will fix it soon.
>>
>> Thanks,
>>
>> Evan
>>
>
> PR2...
2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...We have 16-bit registers class and want to set both the lo and high
parts using INSERT_SUBREG.
The workaround is to declare the same SubRegClass twice while declaring
the SuperRegisterClass. i.e.
def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
let SubRegClassList = [FSR8, FSR8]; // HERE.
}
SubRegSet : <1, [FSR0, FSR1], [FSR0L, FSR0H]>;
SubRegSet : <2, [FSR0, FSR1], [FSR0H, FSR0L]>;
I think the fundamental problem we have there is that we are using
SubIdx for both purposes: 1. to enumerate over subregister classses, 2.
To enumerate subregs of the s...
2008 Oct 20
0
[LLVMdev] INSERT_SUBREG node.
...jiv gupta wrote:
>>>
>>> PR2916 filed.
>>> Though I did not quite understand why this could be a tablegen bug?
>>
>>
>> Based on your comments. :-) It should be possible to specify two FSR0
>> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
>> workaround you described:
>>
>>
>> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
>> let SubRegClassList = [FSR8, FSR8]; // HERE.
>> }
>>
> It is currently possible.
I am confused. Is what you described in PR...
2008 Oct 20
1
[LLVMdev] INSERT_SUBREG node.
...> >>> PR2916 filed.
> >>> Though I did not quite understand why this could be a tablegen bug?
> >>
> >>
> >> Based on your comments. :-) It should be possible to specify two FSR0
> >> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the
> >> workaround you described:
> >>
> >>
> >> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> >> let SubRegClassList = [FSR8, FSR8]; // HERE.
> >> }
> >>
> > It is currently possible.
>...
2008 Oct 16
0
[LLVMdev] INSERT_SUBREG node.
...to set both the lo and high
> parts using INSERT_SUBREG.
>
> The workaround is to declare the same SubRegClass twice while
> declaring
> the SuperRegisterClass. i.e.
>
> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> {
> let SubRegClassList = [FSR8, FSR8]; // HERE.
> }
This is a bug, probably in tablegen. Unfortunately I don't have the
time to fix it. But please file a bug about this. Hopefully someone
will fix it soon.
Thanks,
Evan
>
>
> SubRegSet : <1, [FSR0, FSR1], [FSR0L, FSR0H]>;
> SubRegSet : <2, [F...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
...<"FSR1L">;
>>> def FSR1H : Register<"FSR1H">;
>>>
>>> def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>;
>>> def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>;
>>>
>>> def FSR8RC : RegisterClass<"PIC16", [i8], 8, [FSR0L, FSR0H, FSR0L,
>>> FSR1H]>;
>>>
>>> def FSR16RC : RegisterClass<"PIC16", [i16], 8, [FSR0, FSR1]> {
>>> let SubRegClassList = [FSR8RC];
>>> }
>>>
>>> in my ca...
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
...R1L : Register<"FSR1L">;
> > def FSR1H : Register<"FSR1H">;
> >
> > def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>;
> > def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>;
> >
> > def FSR8RC : RegisterClass<"PIC16", [i8], 8, [FSR0L, FSR0H, FSR0L,
> > FSR1H]>;
> >
> > def FSR16RC : RegisterClass<"PIC16", [i16], 8, [FSR0, FSR1]> {
> > let SubRegClassList = [FSR8RC];
> > }
> >
> > in my case I want to inser...