Displaying 8 results from an estimated 8 matches for "fsr1l".
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fsr0l
2008 Oct 13
2
[LLVMdev] INSERT_SUBREG node.
...to do it is:
>
>
> v4 = insert_subreg implicit_def, v1, 0
> v3 = insert_subreg v4, v2, 1
>
>
> Evan
>
This is how my register classes look like:
def FSR0L : Register<"FSR0L">;
def FSR0H : Register<"FSR0H">;
def FSR1L : Register<"FSR1L">;
def FSR1H : Register<"FSR1H">;
def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>;
def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>;
def FSR8RC : RegisterClass<"PIC16", [i8], 8, [F...
2008 Oct 14
0
[LLVMdev] INSERT_SUBREG node.
...ert_subreg implicit_def, v1, 0
>> v3 = insert_subreg v4, v2, 1
>>
>>
>> Evan
>>
>
> This is how my register classes look like:
>
> def FSR0L : Register<"FSR0L">;
> def FSR0H : Register<"FSR0H">;
> def FSR1L : Register<"FSR1L">;
> def FSR1H : Register<"FSR1H">;
>
> def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>;
> def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>;
>
> def FSR8RC : RegisterClass<"...
2008 Oct 15
2
[LLVMdev] INSERT_SUBREG node.
...t_subreg v4, v2, 1
> >>
> >>
> >> Evan
> >>
> >
> > This is how my register classes look like:
> >
> > def FSR0L : Register<"FSR0L">;
> > def FSR0H : Register<"FSR0H">;
> > def FSR1L : Register<"FSR1L">;
> > def FSR1H : Register<"FSR1H">;
> >
> > def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>;
> > def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>;
> >
> > def FSR...
2008 Oct 15
0
[LLVMdev] INSERT_SUBREG node.
...v2, 1
>>>>
>>>>
>>>> Evan
>>>>
>>>
>>> This is how my register classes look like:
>>>
>>> def FSR0L : Register<"FSR0L">;
>>> def FSR0H : Register<"FSR0H">;
>>> def FSR1L : Register<"FSR1L">;
>>> def FSR1H : Register<"FSR1H">;
>>>
>>> def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>;
>>> def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>;
>>>
>&g...
2008 Oct 02
0
[LLVMdev] INSERT_SUBREG node.
On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote:
> What’s the value produced by an INSERT_SUBREG node? Is it a chain?
No, insert_subreg returns a value:
v1 = insert_subreg v2, v3, idx
v1 and v2 will have the same type, e.g. i16, and v3 must have a sub-
register type, e.g. i8.
> Can I use to set a superreg of i16 type with two i8 values, and use
> the supperreg as
2008 Oct 02
2
[LLVMdev] INSERT_SUBREG node.
What's the value produced by an INSERT_SUBREG node? Is it a chain?
Can I use to set a superreg of i16 type with two i8 values, and use the
supperreg as an operand somewhere else?
- Sanjiv
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2008 Oct 15
3
[LLVMdev] INSERT_SUBREG node.
...;
> >>>> Evan
> >>>>
> >>>
> >>> This is how my register classes look like:
> >>>
> >>> def FSR0L : Register<"FSR0L">;
> >>> def FSR0H : Register<"FSR0H">;
> >>> def FSR1L : Register<"FSR1L">;
> >>> def FSR1H : Register<"FSR1H">;
> >>>
> >>> def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>;
> >>> def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>;...
2008 Oct 16
0
[LLVMdev] INSERT_SUBREG node.
...t; Evan
>>>>>>
>>>>>
>>>>> This is how my register classes look like:
>>>>>
>>>>> def FSR0L : Register<"FSR0L">;
>>>>> def FSR0H : Register<"FSR0H">;
>>>>> def FSR1L : Register<"FSR1L">;
>>>>> def FSR1H : Register<"FSR1H">;
>>>>>
>>>>> def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>;
>>>>> def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H,...