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...aking > use of insert_subreg, no? > > Evan > it is, though we have a workaround. We have 16-bit registers class and want to set both the lo and high parts using INSERT_SUBREG. The workaround is to declare the same SubRegClass twice while declaring the SuperRegisterClass. i.e. def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { let SubRegClassList = [FSR8, FSR8]; // HERE. } SubRegSet : <1, [FSR0, FSR1], [FSR0L, FSR0H]>; SubRegSet : <2, [FSR0, FSR1], [FSR0H, FSR0L]>; I think the fundamental problem we have there is that we are using SubI...

...an >> > it is, though we have a workaround. > > We have 16-bit registers class and want to set both the lo and high > parts using INSERT_SUBREG. > > The workaround is to declare the same SubRegClass twice while > declaring > the SuperRegisterClass. i.e. > > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { > let SubRegClassList = [FSR8, FSR8]; // HERE. > } This is a bug, probably in tablegen. Unfortunately I don't have the time to fix it. But please file a bug about this. Hopefully someone will fix it soon. Thanks,...

...to do it is: > > > v4 = insert_subreg implicit_def, v1, 0 > v3 = insert_subreg v4, v2, 1 > > > Evan > This is how my register classes look like: def FSR0L : Register<"FSR0L">; def FSR0H : Register<"FSR0H">; def FSR1L : Register<"FSR1L">; def FSR1H : Register<"FSR1H">; def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>; def FSR8RC : RegisterClass<"PIC16", [i8], 8, [...

...t_subreg v4, v2, 1 > >> > >> > >> Evan > >> > > > > This is how my register classes look like: > > > > def FSR0L : Register<"FSR0L">; > > def FSR0H : Register<"FSR0H">; > > def FSR1L : Register<"FSR1L">; > > def FSR1H : Register<"FSR1H">; > > > > def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; > > def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>; > > > > def FS...

...v2, 1 >>>> >>>> >>>> Evan >>>> >>> >>> This is how my register classes look like: >>> >>> def FSR0L : Register<"FSR0L">; >>> def FSR0H : Register<"FSR0H">; >>> def FSR1L : Register<"FSR1L">; >>> def FSR1H : Register<"FSR1H">; >>> >>> def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; >>> def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>; >>> >&...

...around. > > > > We have 16-bit registers class and want to set both the lo and high > > parts using INSERT_SUBREG. > > > > The workaround is to declare the same SubRegClass twice while > > declaring > > the SuperRegisterClass. i.e. > > > > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { > > let SubRegClassList = [FSR8, FSR8]; // HERE. > > } > > This is a bug, probably in tablegen. Unfortunately I don't have the > time to fix it. But please file a bug about this. Hopefully someone &...

...ert_subreg implicit_def, v1, 0 >> v3 = insert_subreg v4, v2, 1 >> >> >> Evan >> > > This is how my register classes look like: > > def FSR0L : Register<"FSR0L">; > def FSR0H : Register<"FSR0H">; > def FSR1L : Register<"FSR1L">; > def FSR1H : Register<"FSR1H">; > > def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; > def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>; > > def FSR8RC : RegisterClass<&quot...

...>> We have 16-bit registers class and want to set both the lo and high >>> parts using INSERT_SUBREG. >>> >>> The workaround is to declare the same SubRegClass twice while >>> declaring >>> the SuperRegisterClass. i.e. >>> >>> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { >>> let SubRegClassList = [FSR8, FSR8]; // HERE. >>> } >> >> This is a bug, probably in tablegen. Unfortunately I don't have the >> time to fix it. But please file a bug about this. Hopeful...

...gt; > > > high > > > > parts using INSERT_SUBREG. > > > > > > > > The workaround is to declare the same SubRegClass twice while > > > > declaring > > > > the SuperRegisterClass. i.e. > > > > > > > > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { > > > > let SubRegClassList = [FSR8, FSR8]; // HERE. > > > > } > > > > > > This is a bug, probably in tablegen. Unfortunately I don't have > > > the > > > time to...

On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote: > What’s the value produced by an INSERT_SUBREG node? Is it a chain? No, insert_subreg returns a value: v1 = insert_subreg v2, v3, idx v1 and v2 will have the same type, e.g. i16, and v3 must have a sub- register type, e.g. i8. > Can I use to set a superreg of i16 type with two i8 values, and use > the supperreg as

What's the value produced by an INSERT_SUBREG node? Is it a chain? Can I use to set a superreg of i16 type with two i8 values, and use the supperreg as an operand somewhere else? - Sanjiv -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20081002/f07bc88c/attachment.html>

...id not quite understand why this could be a tablegen bug? >> >> >> Based on your comments. :-) It should be possible to specify two FSR0 >> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the >> workaround you described: >> >> >> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { >> let SubRegClassList = [FSR8, FSR8]; // HERE. >> } >> > It is currently possible. I am confused. Is what you described in PR2916 an issue or not? Evan > > > - Sanjiv > >> >> Evan...

...e a tablegen bug? > >> > >> > >> Based on your comments. :-) It should be possible to specify two FSR0 > >> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the > >> workaround you described: > >> > >> > >> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { > >> let SubRegClassList = [FSR8, FSR8]; // HERE. > >> } > >> > > It is currently possible. > > I am confused. Is what you described in PR2916 an issue or not? > is specifying the same...