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...parts using INSERT_SUBREG. The workaround is to declare the same SubRegClass twice while declaring the SuperRegisterClass. i.e. def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { let SubRegClassList = [FSR8, FSR8]; // HERE. } SubRegSet : <1, [FSR0, FSR1], [FSR0L, FSR0H]>; SubRegSet : <2, [FSR0, FSR1], [FSR0H, FSR0L]>; I think the fundamental problem we have there is that we are using SubIdx for both purposes: 1. to enumerate over subregister classses, 2. To enumerate subregs of the same type of a super reg. - Sanjiv. > > > > > > &...

...air of i8 v1, v2 to create a i16 v3. The > way to do it is: > > > v4 = insert_subreg implicit_def, v1, 0 > v3 = insert_subreg v4, v2, 1 > > > Evan > This is how my register classes look like: def FSR0L : Register<"FSR0L">; def FSR0H : Register<"FSR0H">; def FSR1L : Register<"FSR1L">; def FSR1H : Register<"FSR1H">; def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]>; def FSR8RC...

...insert_subreg implicit_def, v1, 0 > >> v3 = insert_subreg v4, v2, 1 > >> > >> > >> Evan > >> > > > > This is how my register classes look like: > > > > def FSR0L : Register<"FSR0L">; > > def FSR0H : Register<"FSR0H">; > > def FSR1L : Register<"FSR1L">; > > def FSR1H : Register<"FSR1H">; > > > > def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; > > def FSR1 : RegisterWithSubRegs<"FS...

...v1, 0 >>>> v3 = insert_subreg v4, v2, 1 >>>> >>>> >>>> Evan >>>> >>> >>> This is how my register classes look like: >>> >>> def FSR0L : Register<"FSR0L">; >>> def FSR0H : Register<"FSR0H">; >>> def FSR1L : Register<"FSR1L">; >>> def FSR1H : Register<"FSR1H">; >>> >>> def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; >>> def FSR1 : RegisterWithSubRegs&...

...way to do it is: >> >> >> v4 = insert_subreg implicit_def, v1, 0 >> v3 = insert_subreg v4, v2, 1 >> >> >> Evan >> > > This is how my register classes look like: > > def FSR0L : Register<"FSR0L">; > def FSR0H : Register<"FSR0H">; > def FSR1L : Register<"FSR1L">; > def FSR1H : Register<"FSR1H">; > > def FSR0 : RegisterWithSubRegs<"FSR0", [FSR0H, FSR0L]>; > def FSR1 : RegisterWithSubRegs<"FSR1", [FSR1H, FSR1L]&...

...t; { > let SubRegClassList = [FSR8, FSR8]; // HERE. > } This is a bug, probably in tablegen. Unfortunately I don't have the time to fix it. But please file a bug about this. Hopefully someone will fix it soon. Thanks, Evan > > > SubRegSet : <1, [FSR0, FSR1], [FSR0L, FSR0H]>; > SubRegSet : <2, [FSR0, FSR1], [FSR0H, FSR0L]>; > > > I think the fundamental problem we have there is that we are using > SubIdx for both purposes: 1. to enumerate over subregister > classses, 2. > To enumerate subregs of the same type of a super reg. > >...

On Oct 2, 2008, at 11:02 AM, Sanjiv.Gupta at microchip.com wrote: > What’s the value produced by an INSERT_SUBREG node? Is it a chain? No, insert_subreg returns a value: v1 = insert_subreg v2, v3, idx v1 and v2 will have the same type, e.g. i16, and v3 must have a sub- register type, e.g. i8. > Can I use to set a superreg of i16 type with two i8 values, and use > the supperreg as

What's the value produced by an INSERT_SUBREG node? Is it a chain? Can I use to set a superreg of i16 type with two i8 values, and use the supperreg as an operand somewhere else? - Sanjiv -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20081002/f07bc88c/attachment.html>

...t; > > Thanks, > > > > > > Evan > > > > > > > PR2916 filed. > > Though I did not quite understand why this could be a tablegen bug? > > > Based on your comments. :-) It should be possible to specify two FSR0 > sub-registers (FSR0L, FSR0H of the same register class FSR8) with the > workaround you described: > > > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { > let SubRegClassList = [FSR8, FSR8]; // HERE. > } > It is currently possible. - Sanjiv > > Evan > > &g...

On Oct 20, 2008, at 7:10 AM, sanjiv gupta wrote: >>> >>> PR2916 filed. >>> Though I did not quite understand why this could be a tablegen bug? >> >> >> Based on your comments. :-) It should be possible to specify two FSR0 >> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the >> workaround you described: >> >> >> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { >> let SubRegClassList = [FSR8, FSR8]; // HERE. >> } >> > It is currently possible. I am confu...

...ta wrote: > > >>> > >>> PR2916 filed. > >>> Though I did not quite understand why this could be a tablegen bug? > >> > >> > >> Based on your comments. :-) It should be possible to specify two FSR0 > >> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the > >> workaround you described: > >> > >> > >> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { > >> let SubRegClassList = [FSR8, FSR8]; // HERE. > >> } > >> > &g...

...his. Hopefully someone >> will fix it soon. >> >> Thanks, >> >> Evan >> > > PR2916 filed. > Though I did not quite understand why this could be a tablegen bug? Based on your comments. :-) It should be possible to specify two FSR0 sub-registers (FSR0L, FSR0H of the same register class FSR8) with the workaround you described: def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { let SubRegClassList = [FSR8, FSR8]; // HERE. } Evan > > > - Sanjiv > > > _______________________________________________ > L...

On Thu, 2008-10-16 at 08:55 -0700, Evan Cheng wrote: > On Oct 15, 2008, at 11:21 AM, sanjiv gupta wrote: > > >>> > >> > >> Ok. The AX / AH super-reg and sub-reg relationship is not defined. In > >> general x86 is not making good use of the high 8-bit sub-registers. > >> We > >> are leaving some performance on the table. We'll