Displaying 2 results from an estimated 2 matches for "fsmovapdrr".
2008 Sep 03
2
[LLVMdev] Codegen/Register allocation question.
...ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use>
28 %reg1026<def> = MOV8ri 4
36 %reg1027<def> = FsFLD0SD
44 %reg1028<def> = LEA64r %reg0, 1, %reg0, <ga:.str1>
52 %RDI<def> = MOV64rr %reg1028<kill>
60 %XMM0<def> = FsMOVAPDrr %reg1027
68 %XMM1<def> = FsMOVAPDrr %reg1027
76 %XMM2<def> = FsMOVAPDrr %reg1027
84 %XMM3<def> = FsMOVAPDrr %reg1027<kill>
92 %AL<def> = MOV8rr %reg1026<kill>
100 CALL64pcrel32 <ga:printf>, %RDI<kill>, %XMM0<kill>,
%XMM1&...
2008 Sep 04
0
[LLVMdev] Codegen/Register allocation question.
...mp-def,dead>,
> %ESP<imp-use>
> 28 %reg1026<def> = MOV8ri 4
> 36 %reg1027<def> = FsFLD0SD
> 44 %reg1028<def> = LEA64r %reg0, 1, %reg0, <ga:.str1>
> 52 %RDI<def> = MOV64rr %reg1028<kill>
> 60 %XMM0<def> = FsMOVAPDrr %reg1027
> 68 %XMM1<def> = FsMOVAPDrr %reg1027
> 76 %XMM2<def> = FsMOVAPDrr %reg1027
> 84 %XMM3<def> = FsMOVAPDrr %reg1027<kill>
> 92 %AL<def> = MOV8rr %reg1026<kill>
> 100 CALL64pcrel32 <ga:printf>, %RDI<kill>,...