search for: fsin

Displaying 20 results from an estimated 26 matches for "fsin".

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2005 Apr 29
1
[LLVMdev] Floating point instructions patch
...ready catch this at the DAG level. If we aren't, please let me know. OK, no problem - I was just told last time I tried to get my patch in that this was needed because the C++ frontend generated this code, I'm generating calls to fabsf() so for me this is unimportant ... > 2. Codegen fsin/fcos to fsin/fcos for X86. We cannot do this, except > under the control of something like -enable-unsafe-fp-math. These > instructions are architected to have a limited range. OK, I will add this flag. > 3. Codegen fsqrt/fsqrtf C functions to the FSQRT dag node. These > f...
2005 Apr 28
0
[LLVMdev] Floating point instructions patch
...nstrs: http://mail.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20050425/025894.html The patches I didn't apply are these: 1. Match (Y < 0) ? -Y : Y -> FABS in the SelectionDAGISel.cpp file. We already catch this at the DAG level. If we aren't, please let me know. 2. Codegen fsin/fcos to fsin/fcos for X86. We cannot do this, except under the control of something like -enable-unsafe-fp-math. These instructions are architected to have a limited range. 3. Codegen fsqrt/fsqrtf C functions to the FSQRT dag node. These functions can set errno, so this is not a safe...
2005 Apr 28
3
[LLVMdev] Floating point instructions patch
Hello, I have been gone for a while, finishing work on my Master's thesis... Now that I'm back I updated LLVM to the most recent version and found that my FP_ABS SelectionDAGNode type and code generation was now conflicting with the new FABS node type. I brought the rest of my local modifications in line with the FABS implementation, so here is my patch that includes sqrt, sin and cos
2011 Dec 15
10
fsincos emulation on AMD CPUs
All, in the light of erratum #573 I''m wondering if we need to tweak or conditionally suppress fsincos emulation. The question is whether there is any possibility for getting the emulator to hit this instruction on AMD (as no real mode emulation ought to be taking place there), i.e. whether there are places where emulation gets continued eagerly in anticipation of the need for emulation on a near...
2016 Nov 07
2
About trigonometric Instructions
HI developers, I want to add trigonometric instructions in my instrinfo.td files how can i directly map these instructions in .td files. Please help me Guys.For Sin, Cos, Tan and Cot Instructions. If I used llvm.sin.* as SDNode Then it is error as llvm variable is not defined SO please Help me. Thanks and Regards Varun -------------- next part -------------- An HTML attachment was scrubbed...
2011 Feb 22
1
[LLVMdev] unary floating point operations using clang
Hello, Is there a way of generating unary floating point operations (like ISD::FABS, ISD::FSIN, ...) from C code using clang? I am building a backend for a machine that has hw support for these ops and I need a way to test them. Thanks, Alex -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110222/32cd...
2016 Jun 05
2
Doubts
...r example: setOperationAction(ISD::ADD, MVT::i1, Promote); Is it correct to say that I'm promoting any operand used by the ISD::ADD node to a larger type? If so, what would that value type be? If I use the same function with the expand as the third argument like below: setOperationAction(ISD::FSIN, MVT::f32, Expand); What will the expansion look like, since I don´t provide any custom implementation of the node? Also, what is the meaning of the MVT::f32 in this case? Thanks, Patosga 2016-06-05 19:16 GMT+01:00 Pierre Gagelin <Pierre.Gagelin at myport.ac.uk>: > Hi Patosga, > >...
2012 Feb 08
6
[LLVMdev] Clarifying FMA-related TargetOptions
...d some clarification on the intended semantics for the various FP precision-related TargetOptions. I've summarized the three relevant ones below: UnsafeFPMath - Defaults to off, enables "less precise" results than permitted by IEEE754. Comments specifically reference using hardware FSIN/FCOS on X86. NoExcessFPPrecision - Defaults to off (i.e. excess precision allowed), enables higher-precision implementations than specified by IEEE754. Comments reference FMA-like operations, and X87 without rounding all over the place. LessPreciseFPMADOption - Defaults to off, enables "les...
2005 Jan 04
2
[LLVMdev] Math instructions
Hello, I'm currently adding the floating point math instructions (fabs, fsin, fcos ...) to the x86 instruction set. I'm a bit unsure how to make the back end actually generate these instructions, though. My current plan is to add llvm intrinsics for these instructions but I've noticed that llvm already handles C math library functions to some extent. It feels a...
2016 Jun 06
2
Doubts
...t;> >> Is it correct to say that I'm promoting any operand used by the ISD::ADD >> node to a larger type? If so, what would that value type be? >> >> If I use the same function with the expand as the third argument like >> below: >> setOperationAction(ISD::FSIN, MVT::f32, Expand); >> What will the expansion look like, since I don´t provide any custom >> implementation of the node? Also, what is the meaning of the MVT::f32 in >> this case? >> >> Thanks, >> Patosga >> >> 2016-06-05 19:16 GMT+01:00 Pierre Gagel...
2012 Feb 08
0
[LLVMdev] Clarifying FMA-related TargetOptions
...d some clarification on the intended semantics for the various FP precision-related TargetOptions. I've summarized the three relevant ones below: UnsafeFPMath - Defaults to off, enables "less precise" results than permitted by IEEE754. Comments specifically reference using hardware FSIN/FCOS on X86. NoExcessFPPrecision - Defaults to off (i.e. excess precision allowed), enables higher-precision implementations than specified by IEEE754. Comments reference FMA-like operations, and X87 without rounding all over the place. LessPreciseFPMADOption - Defaults to off, enables "les...
2013 Jan 22
0
[LLVMdev] sincos optimization
On 22/01/13 05:30, Redmond, Paul wrote: [...] > I'm looking at http://llvm.org/bugs/show_bug.cgi?id=13204 which involves converting calls to sin and cos to sincos (when available) > > Initially I thought about transforming calls to sinf/cosf to sincosf. However, I don't think this is a legal transformation given that a declaration for a function called sinf is not necessarily the
2013 Jan 22
1
[LLVMdev] sincos optimization
...It appears that such functions are only promoted if they're declared > readnone, which provides some protection against overriding a standard > library function, but I haven't found anything that explicitly checks > for this yet. > Thanks for the tip. I am able to see sinf to FSIN generation when I compile with -ffast-math. I don't have much experience with the selection dag but I feel like this transformation shouldn't be done at this level (it's more complicated than the transformations done by SelectionDAGCombine) Would it make sense to move library call to...
2005 Apr 29
1
[LLVMdev] Floating point instructions patch
New patch here -- it's not been tested yet because we're having some problems with the application (I can't create new VM programs at the moment), but it compiles OK ;-) Please look over it and see if there are some more changes you'd like me to make before you can commit it... m. -------------- next part -------------- An embedded and charset-unspecified text was scrubbed...
2013 Jan 22
2
[LLVMdev] sincos optimization
Hi, I'm looking at http://llvm.org/bugs/show_bug.cgi?id=13204 which involves converting calls to sin and cos to sincos (when available) Initially I thought about transforming calls to sinf/cosf to sincosf. However, I don't think this is a legal transformation given that a declaration for a function called sinf is not necessarily the standard library function. Therefore it makes sense to
2005 Jan 04
0
[LLVMdev] Math instructions
On Tue, 4 Jan 2005, Morten Ofstad wrote: > I'm currently adding the floating point math instructions (fabs, fsin, fcos > ...) to the x86 instruction set. Cool! > I'm a bit unsure how to make the back end actually generate these > instructions, though. My current plan is to add llvm intrinsics for > these instructions but I've noticed that llvm already handles C math > library func...
2012 Feb 08
0
[LLVMdev] Clarifying FMA-related TargetOptions
...ended semantics for the various FP precision-related > TargetOptions. I've summarized the three relevant ones below: > > > UnsafeFPMath - Defaults to off, enables "less precise" results than > permitted by IEEE754. Comments specifically reference using hardware > FSIN/FCOS on X86. > > > NoExcessFPPrecision - Defaults to off (i.e. excess precision allowed), > enables higher-precision implementations than specified by IEEE754. > Comments reference FMA-like operations, and X87 without rounding all > over the place. > > > LessPreciseF...
2016 Jun 05
3
Doubts
Hello sir, I'm having some problems understading how llvm works. I'm following a concrete example and visualizing the DAG and the .s output and some stuff doesn´t seem to match. I sorry to bother you but I don´t know where I can expose my doubts and I wonder if you could redirect me to some discussion place where someone might help me. Thanks, Patosga
2016 Jun 07
2
Doubts
...t I'm promoting any operand used by the ISD::ADD >>>> node to a larger type? If so, what would that value type be? >>>> >>>> If I use the same function with the expand as the third argument like >>>> below: >>>> setOperationAction(ISD::FSIN, MVT::f32, Expand); >>>> What will the expansion look like, since I don´t provide any custom >>>> implementation of the node? Also, what is the meaning of the MVT::f32 in >>>> this case? >>>> >>>> Thanks, >>>> Patosga >>&...
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...+ case ISD::CTTZ: + case ISD::CTLZ: + case ISD::CTPOP: + case ISD::SELECT: + case ISD::SELECT_CC: + case ISD::SINT_TO_FP: + case ISD::UINT_TO_FP: + case ISD::FP_TO_SINT: + case ISD::FP_TO_UINT: + case ISD::FNEG: + case ISD::FABS: + case ISD::FSQRT: + case ISD::FSIN: + case ISD::FCOS: + case ISD::FPOWI: + case ISD::FPOW: + case ISD::FLOG: + case ISD::FLOG2: + case ISD::FLOG10: + case ISD::FEXP: + case ISD::FEXP2: + case ISD::FCEIL: + case ISD::FTRUNC: + case ISD::FRINT: + case ISD::FNEARBYINT: + case ISD::FFLOOR: + s...