search for: fsfld0sd

...xmm0, %xmm0 testl %esi, %esi je .LBB0_2 # BB#1: xorps %xmm0, %xmm0 addsd (%rdi), %xmm0 .LBB0_2: ret ... Note that there are 2 xorps instructions, the one in BB#1 being clearly redundant as it's dominated by the first one. Two xorps come from 2 FsFLD0SD generated by instruction selection and never eliminated by machine passes. My guess would be machine CSE should take care of it. A variation of this case without indirection shows the same problem, as well as not commuting addps, resulting in an extra movps: $ cat t.c double f(double p, int n) {...

...ion: entry: 4 %reg1024<def,dead> = MOV32rr %EDI<kill> 12 %reg1025<def,dead> = MOV64rr %RSI<kill> 20 ADJCALLSTACKDOWN 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, %ESP<imp-use> 28 %reg1026<def> = MOV8ri 4 36 %reg1027<def> = FsFLD0SD 44 %reg1028<def> = LEA64r %reg0, 1, %reg0, <ga:.str1> 52 %RDI<def> = MOV64rr %reg1028<kill> 60 %XMM0<def> = FsMOVAPDrr %reg1027 68 %XMM1<def> = FsMOVAPDrr %reg1027 76 %XMM2<def> = FsMOVAPDrr %reg1027 84 %XMM3<def> = FsMOV...

...24<def,dead> = MOV32rr %EDI<kill> > 12 %reg1025<def,dead> = MOV64rr %RSI<kill> > 20 ADJCALLSTACKDOWN 0, %ESP<imp-def>, %EFLAGS<imp-def,dead>, > %ESP<imp-use> > 28 %reg1026<def> = MOV8ri 4 > 36 %reg1027<def> = FsFLD0SD > 44 %reg1028<def> = LEA64r %reg0, 1, %reg0, <ga:.str1> > 52 %RDI<def> = MOV64rr %reg1028<kill> > 60 %XMM0<def> = FsMOVAPDrr %reg1027 > 68 %XMM1<def> = FsMOVAPDrr %reg1027 > 76 %XMM2<def> = FsMOVAPDrr %reg1027 > 84...

...pressure. Of course, with such a small testcase, register pressure isn't a problem. MachineCSE might be able to do a better job here. Nick Note that there are 2 xorps instructions, the one in BB#1 being clearly > redundant > as it's dominated by the first one. Two xorps come from 2 FsFLD0SD > generated by > instruction selection and never eliminated by machine passes. My guess > would be > machine CSE should take care of it. > > A variation of this case without indirection shows the same problem, as > well as > not commuting addps, resulting in an extra movps:...