Displaying 7 results from an estimated 7 matches for "frint".
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2013 Jun 19
1
[LLVMdev] round() vs. rint()/nearbyint() with fast-math
Hello,
Sometime over the last few months, I implemented in the PowerPC backend a fast-math-only optimization which lowers ISD::FRINT/FNEARBYINT in terms of the frin instruction (when supported). As one of my users has pointed out to me, frin actually implements the semantics of round() [it ties away from zero] instead of implementing nearbyint() [which ties to even]. This user has additionally pointed out that LLVM on x86 does n...
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...G:
+ case ISD::FABS:
+ case ISD::FSQRT:
+ case ISD::FSIN:
+ case ISD::FCOS:
+ case ISD::FPOWI:
+ case ISD::FPOW:
+ case ISD::FLOG:
+ case ISD::FLOG2:
+ case ISD::FLOG10:
+ case ISD::FEXP:
+ case ISD::FEXP2:
+ case ISD::FCEIL:
+ case ISD::FTRUNC:
+ case ISD::FRINT:
+ case ISD::FNEARBYINT:
+ case ISD::FFLOOR:
+ switch (TLI.getOperationAction(I->getOpcode(), I->getValueType(0))) {
+ case TargetLowering::Promote:
+ Result = PromoteVectorOp(SDValue(Result, 0)).getNode();
+ break;
+ case TargetLowering::Legal: break;
+...
2009 May 20
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...G:
+ case ISD::FABS:
+ case ISD::FSQRT:
+ case ISD::FSIN:
+ case ISD::FCOS:
+ case ISD::FPOWI:
+ case ISD::FPOW:
+ case ISD::FLOG:
+ case ISD::FLOG2:
+ case ISD::FLOG10:
+ case ISD::FEXP:
+ case ISD::FEXP2:
+ case ISD::FCEIL:
+ case ISD::FTRUNC:
+ case ISD::FRINT:
+ case ISD::FNEARBYINT:
+ case ISD::FFLOOR:
+ switch (TLI.getOperationAction(I->getOpcode(), I->getValueType(0))) {
+ case TargetLowering::Promote:
+ Result = PromoteVectorOp(SDValue(Result, 0)).getNode();
+ break;
+ case TargetLowering::Legal: break;
+...
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...G:
+ case ISD::FABS:
+ case ISD::FSQRT:
+ case ISD::FSIN:
+ case ISD::FCOS:
+ case ISD::FPOWI:
+ case ISD::FPOW:
+ case ISD::FLOG:
+ case ISD::FLOG2:
+ case ISD::FLOG10:
+ case ISD::FEXP:
+ case ISD::FEXP2:
+ case ISD::FCEIL:
+ case ISD::FTRUNC:
+ case ISD::FRINT:
+ case ISD::FNEARBYINT:
+ case ISD::FFLOOR:
+ switch (TLI.getOperationAction(I->getOpcode(), I->getValueType(0))) {
+ case TargetLowering::Promote:
+ Result = PromoteVectorOp(SDValue(Result, 0)).getNode();
+ break;
+ case TargetLowering::Legal: break;
+...
2012 Jul 16
3
[LLVMdev] RFC: LLVM incubation, or requirements for committing new backends
...nAction(ISD::SELECT_CC, MVT::i32, Custom);
> +
> + // Library functions. These default to Expand, but we have instructions
> + // for them.
> + setOperationAction(ISD::FCEIL, MVT::f32, Legal);
> + setOperationAction(ISD::FEXP2, MVT::f32, Legal);
> + setOperationAction(ISD::FRINT, MVT::f32, Legal);
> +
> + setOperationAction(ISD::UDIV, MVT::i32, Expand);
> + setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
> + setOperationAction(ISD::UREM, MVT::i32, Expand);
> +}
> +
> +SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DA...