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Hello Andy, I want to use the existing scheduling models to estimate performance on a subtarget. For that, I am looking at the new llvm-mca tool where they only use SchedReadWrite and state that not supporting Instruction Itineraries is a limitation. I have also read that the Instruction Itineraries allow to model certain things which cannot be represented in the SchedReadWrite however, I am

...node and has > fairly straightforward semantics - it's a store node. So for example a DAG > that looks like: > (store i64:$src, addr:$dst) > actually says store the 64-bit integer $src at address $dst. > > Nemanja > > On Mon, Jun 6, 2016 at 5:16 PM, Pedro Lopes <pedro.fraiao at gmail.com> wrote: >> >> Thanks, indeed it was on the LegalizeDAG.cpp and the information proved >> very useful. >> >> I also realized that the customization, promotion or expansion will occur >> whenever any operand, with the same type as the type specified...

Hi, I am having some trouble understanding the scheduling scheme for the C-A9. Looking at the ARMScheduleA9.td file I find this line that overrides the target SchedWrite with processor specific latencies. def : SchedAlias<WriteALU, A9WriteALU>; However, in this same file, I find the lines presented below, which are mapping the SchedReadWrite to, for example, the ANDri instruction. //

Thanks, indeed it was on the LegalizeDAG.cpp and the information proved very useful. I also realized that the customization, promotion or expansion will occur whenever any operand, with the same type as the type specified on the second argument (MVT) of setOperationAction function, appears. (Correct me if I'm wrong). The second doubt I have regards instruction matching. When I define a