Displaying 9 results from an estimated 9 matches for "fragdepth".
2014 Jun 23
1
[PATCH v3] nv50/ir: make ARB_viewport_array behave like it does with other drivers
...llium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -177,6 +177,7 @@ struct nv50_ir_prog_info
uint8_t vertexId; /* system value index of VertexID */
uint8_t edgeFlagIn;
uint8_t edgeFlagOut;
+ int8_t viewportId; /* output index of ViewportId */
uint8_t fragDepth; /* output index of FragDepth */
uint8_t sampleMask; /* output index of SampleMask */
boolean sampleInterp; /* perform sample interp on all fp inputs */
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv5...
2014 Jun 23
1
[PATCH v2] nv50/ir: make ARB_viewport_array behave like it does with other drivers
...allium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -177,6 +177,7 @@ struct nv50_ir_prog_info
uint8_t vertexId; /* system value index of VertexID */
uint8_t edgeFlagIn;
uint8_t edgeFlagOut;
+ int8_t viewportId; /* output index of ViewportId */
uint8_t fragDepth; /* output index of FragDepth */
uint8_t sampleMask; /* output index of SampleMask */
boolean sampleInterp; /* perform sample interp on all fp inputs */
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv5...
2009 Sep 12
0
[PATCH 10/13] nv50: proper linkage between VP and FP
...-position inputs and of non-flat
+ * non-position inputs for FP_INTERPOLANT_CTRL
+ */
+ p->cfg.regs[1] |= aid - m;
+ if (flat_nr) {
+ i = p->cfg.io[pc->attr_nr - flat_nr - 1].hw_id;
+ p->cfg.regs[1] |= (i - m) << 16;
} else {
- /* type == PIPE_SHADER_FRAGMENT
- * FragDepth is always first TGSI and last HW output
- */
- int rid = 0;
- i = pc->p->info.writes_z ? 4 : 0;
+ assert(!(p->cfg.regs[1] & 0x0000ff00));
+ p->cfg.regs[1] |= p->cfg.regs[1] << 16;
+ }
- for (; i < pc->result_nr * 4; i++)
- pc->result[i].rhw = rid...
2014 Jun 23
1
[PATCH] nv50/ir: make ARB_viewport_array behave like it does with other drivers
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
---
.../drivers/nouveau/codegen/nv50_ir_driver.h | 1 +
.../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 27 ++++++++++++++++++++--
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
2009 Sep 12
0
[PATCH 09/13] nv50: move allocation of pc regs
...= rid++;
- }
- }
-
- if (depr != 0xffff)
- pc->result[depr*4+2].rhw = rid++;
- }
- }
-
- if (pc->param_nr) {
- int rid = 0;
-
- pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg));
- if (!pc->param)
- goto out_err;
+ /* type == PIPE_SHADER_FRAGMENT
+ * FragDepth is always first TGSI and last HW output
+ */
+ int rid = 0;
+ i = pc->p->info.writes_z ? 4 : 0;
- for (i = 0; i < pc->param_nr; i++) {
- for (c = 0; c < 4; c++, rid++)
- ctor_reg(&pc->param[rid], P_CONST, i, rid);
+ for (; i < pc->result_nr * 4; i++)
+...
2016 Oct 16
2
[PATCH] exa: add GM10x acceleration support
...00, /* FP_INTERP[0x1c0] */
+ 0x00000000, /* FP_INTERP[0x200] */
+ 0x00000000, /* FP_INTERP[0x240] */
+ 0x00000000, /* FP_INTERP[0x280] */
+ 0x00000000, /* FP_INTERP[0x2c0] */
+ 0x00000000, /* FP_INTERP[0x300] */
+ 0x00000000,
+ 0x0000000f, /* FP_RESULT_MASK (0x8000 Face ?) */
+ 0x00000000, /* 0x2 = FragDepth, 0x1 = SampleMask */
+#include "exacanv110.fpc"
+};
+#else
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa pass $r0 a[0x7c] 0x0 0x0 0x1
+mufu rcp $r0 $r0
+ipa $r3 a[0x94] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r2 a[0x90] $r0 0x0 0x1
+tex nodep $r4 $r2 0x0 0x1 t2d 0xf
+ipa $r1 a[0x84...
2016 Oct 27
0
[PATCH v2 1/7] exa: add GM10x acceleration support
...00, /* FP_INTERP[0x1c0] */
+ 0x00000000, /* FP_INTERP[0x200] */
+ 0x00000000, /* FP_INTERP[0x240] */
+ 0x00000000, /* FP_INTERP[0x280] */
+ 0x00000000, /* FP_INTERP[0x2c0] */
+ 0x00000000, /* FP_INTERP[0x300] */
+ 0x00000000,
+ 0x0000000f, /* FP_RESULT_MASK (0x8000 Face ?) */
+ 0x00000000, /* 0x2 = FragDepth, 0x1 = SampleMask */
+#include "exacanv110.fpc"
+};
+#else
+
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa pass $r0 a[0x7c] 0x0 0x0 0x1
+mufu rcp $r0 $r0
+ipa $r3 a[0x94] $r0 0x0 0x1
+sched (st 0x0) (st 0x0) (st 0x0)
+ipa $r2 a[0x90] $r0 0x0 0x1
+tex nodep $r4 $r2 0x0 0x1 t2d 0xf
+ipa $r1 a[0x84...
2016 Oct 17
0
[PATCH] exa: add GM10x acceleration support
...0000, /* FP_INTERP[0x200] */
> + 0x00000000, /* FP_INTERP[0x240] */
> + 0x00000000, /* FP_INTERP[0x280] */
> + 0x00000000, /* FP_INTERP[0x2c0] */
> + 0x00000000, /* FP_INTERP[0x300] */
> + 0x00000000,
> + 0x0000000f, /* FP_RESULT_MASK (0x8000 Face ?) */
> + 0x00000000, /* 0x2 = FragDepth, 0x1 = SampleMask */
> +#include "exacanv110.fpc"
> +};
> +#else
> +
> +sched (st 0x0) (st 0x0) (st 0x0)
> +ipa pass $r0 a[0x7c] 0x0 0x0 0x1
> +mufu rcp $r0 $r0
> +ipa $r3 a[0x94] $r0 0x0 0x1
> +sched (st 0x0) (st 0x0) (st 0x0)
> +ipa $r2 a[0x90] $r0 0x0 0x1...
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
I believe I've addressed all the feedback from the first time around, and
also made fixes necessary for GM20x based on testing results. I believe
now it should actually work for all GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update