Displaying 3 results from an estimated 3 matches for "fpuaoffsetoperand".
2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
...teger32.
Sadly my target only provide native instruction on high and low parts of 32 bits registers.
So, I have to generate a sequence of two native instructions (LOR followed by HOR).
I've introduced an Pseudo instruction with a custom inserter.
def OR_A_oo : CLPPseudoInst<(ins FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB),(outs FPUaROUTADDRegisterClass:$FA_ROUTADD),
[], [RFLAGA],
"# OR_A_oo",...
2017 Jul 27
2
Are there some strong naming conventions in TableGen?
...<ST2[%ptr2](align=4)> t0, Constant:i16<3>, FrameIndex:i16<1>, undef:i16
I have defined the following instruction and associated DAG pattern.
def MOVSUTO_A_i32o : CLPFPU_A_i32o_Inst<0b1000001101,
(ins IMM16Operand:$ImmA,FPUaOffsetOperand:$OffsetB),
(outs ),
[],
"movsuto_a\t$ImmA,$OffsetB","I32O",
[(store (i16 IMM16Operand:$...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...ining only FA_ROUTMUL.
During the instruction lowering, in order to avoid frequent spill out of FA_ROUTMUL, I systematically copy the result of FMUL_A_oo to a virtual register through a COPY_TO_REGCLASS.
def : Pat<(fdiv f32:$OffsetA, f32:$OffsetB), (COPY_TO_REGCLASS (FDIV_A_oo FPUaOffsetOperand:$OffsetA,FPUaOffsetOperand:$OffsetB),FPUaOffsetClass)>;
The instruction lowering goes as expected all instances of FMUL_A_oo are followed by a COPY, freeing the usage of FPUaROUTMULRegisterClass.
These COPY are at positions 64B and 112B in the example below. So far, so good.
My problem arise i...