Displaying 3 results from an estimated 3 matches for "fpsid".
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psid
2015 Sep 17
2
Register Number
...ar register. The 0x01 would be the
encoding used in generating the binary.
The D0 has id 14 on ARM because there are 13 other registers preceding it:
namespace ARM {
enum {
NoRegister,
APSR = 1,
APSR_NZCV = 2,
CPSR = 3,
FPEXC = 4,
FPINST = 5,
FPSCR = 6,
FPSCR_NZCV = 7,
FPSID = 8,
ITSTATE = 9,
LR = 10,
PC = 11,
SP = 12,
SPSR = 13,
D0 = 14,
...
-Krzysztof
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2015 Sep 17
2
Register Number
Dear all,
in my TestRegisterInfo.td file, I defined a register like this:
class TestReg<bits<6> enc, string name> : Register<name> {
let HWEncoding{5-0} = enc;
let Namespace = "TEST";
}
def D0 : TestReg<0x01, "d0">, DwarfRegNum<[1]>;
but when I compile, the result I have in TestGenAsmMatcher.inc is this:
case 'd': // 7
2013 May 30
9
[PATCH v2 0/2] Implement VFP context switch for arm32
Hello,
This is the second version of this patch series.
I only implement the VPF context switch support for arm32 and add dummy function
to avoid compilation on arm64.
I have switched the order of the patch because the old second one can be applied
alone and the patch are cleaner :).
For all the changes see each patch.
Cheers,
Julien Grall (2):
xen/arm: don''t enable VFP on XEN