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Hi Andrew, I seem to be making good progress on the P5600 scheduler using the new machine model but I've got a few questions about it. How would you represent an instruction that splits into two micro-ops and is dispatched to two different reservation stations? For example, I have two reservation stations (AGQ and FPQ). An FPU load instruction is split into a load micro-op which is

...t). Forcing all this information into a single SchedWriteRes def would look like this: def P5600FLD : SchedWriteRes <[P5600UnitAGQ, P5600UnitFP]> { let Latency = 5; // 4 cycle load + 1 cycle FP writeback let NumMicroOps = 2; } This is bad (for an in-order processor) because it prevents FPLoad + FPx from being scheduled in the same cycle and fails to detect a conflict on FP ops 5 scheduled cycles ahead. A better way to express it would be: def P5600LD <[P5600UnitAGQ]> { let Latency = 4; } def P5600FP <[P5600UnitFP]>; def P5600FLD : WriteSequence<[P5600LD, P5600FP]>;...