search for: fpgeneral

...[(set $dst, (Op $src1, $src2))]>; >From the PPC changes, I see that this is already possible under a slightly different form: def FSUBS : AForm_2<59, 20, (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB), "fsubs $FRT, $FRA, $FRB", FPGeneral, - [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>; + [(set f32:$FRT, (fsub f32:$FRA, f32:$FRB))]>; Sebastian -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Jakob Stoklund Olesen wrote: > I have updated TableGen to support a new format for instruction selection patterns. > > Before: > > def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>; > > After: > > def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; > > Since the pattern matching happens on a DAG with type labels, not

...lt;[FPContractions]>; The unique feature of this parttern is that it maps a pair of LLVM IR instructions into a single PPC instruction. def FNMSUBS : AForm_1<59, 30,(outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral, [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),F4RC:$FRB)))]>, Requires<[FPContractions]>; Now I wrote a little toy program that, when compiled, uses this instruction. Here is the program: #include<stdio.h> int main() { float...

I have updated TableGen to support a new format for instruction selection patterns. Before: def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>; After: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; Since the pattern matching happens on a DAG with type labels, not register classes, I think it makes more sense to specify types directly on the input

...[AGEN]>, InstrStage<1, [CRD]>, InstrStage<2, [LWB]>], [9, 5, 5], [NoBypass, GPR_Bypass, GPR_Bypass]>, the add is covered by the itinerary: InstrItinData<FPGeneral , [InstrStage<1, [IFTH1, IFTH2]>, InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [FRACC]>, InstrStage<1, [FEXE1]>,...

...e<1, [IEXE2]>, >>>>>> + InstrStage<1, [IWB]>], >>>>>> + [8, 4], >>>>>> + [NoBypass, GPR_Bypass]>, >>>>>> + InstrItinData<FPGeneral , [InstrStage<1, [IFTH1, IFTH2]>, >>>>>> + InstrStage<1, [PDCD1, PDCD2]>, >>>>>> + InstrStage<1, [DISS1, DISS2]>, >>>>>> + InstrStage&l...