search for: fpcctoarmcc

...ot;ADD" to "ADDS"( provided we somehow determine that we need ADDS here), then everything else related to ARM instruction generation has been handled in current infrastructure. Is this correct or do we need to modify other things also? 2. In file ARMISelLowering.cpp, inside function FPCCtoARMCC, condition ISD::SETO generates ARMCC::VC ( Overflow clear) condition. Thus, if we are able to appropriately generate ISD::SETO inside SDNode for overflow clear and then map it to ARMCC::VC instruction in IntCCtoARMCC, then will that be enough to generate the an instruction like "addvc"?...

...right fix is to add a pass to optimize away the cmp instruction by *folding* it in the preceding add when it's legal. Ideally this will be a target independent pass that x86 and other targets can take advantage of as well. > > > 2. In file ARMISelLowering.cpp, inside function FPCCtoARMCC, > condition ISD::SETO generates ARMCC::VC ( Overflow clear) condition. > Thus, if we are able to appropriately generate ISD::SETO inside > SDNode for overflow clear and then map it to ARMCC::VC instruction > in IntCCtoARMCC, then will that be enough to generate the an > in...

On Jul 14, 2008, at 12:59 PM, kapil anand wrote: > Hi all, > > I am using LLVM compiler and CodeGen for generating ARM binaries. > > I was going through the code for ARM backend. I noticed that the ARM > Condition field( Bits 31-28) is generated by converting the > conditions used in icmp and branch. For example, if I have following > C Code > > int a,b,c,d;

Hi all, I am using LLVM compiler and CodeGen for generating ARM binaries. I was going through the code for ARM backend. I noticed that the ARM Condition field( Bits 31-28) is generated by converting the conditions used in icmp and branch. For example, if I have following C Code int a,b,c,d; c = a+b; if(c==0) d = a + 10; Then I get ( Assembly Instructions with opcodes only) add *cmp*

...is to > add a pass to optimize away the cmp instruction by *folding* it in the > preceding add when it's legal. Ideally this will be a target independent > pass that x86 and other targets can take advantage of as well. > > > > 2. In file ARMISelLowering.cpp, inside function FPCCtoARMCC, condition > ISD::SETO generates ARMCC::VC ( Overflow clear) condition. Thus, if we are > able to appropriately generate ISD::SETO inside SDNode for overflow clear > and then map it to ARMCC::VC instruction in IntCCtoARMCC, then will that be > enough to generate the an instruction like...